MAX1645-MAX1645A Maxim, MAX1645-MAX1645A Datasheet - Page 31

• Manufacturer Part Number: MAX1645-MAX1645A
• Description: Advanced Chemistry-Independent / Level 2 Battery Chargers with Input Current Limiting
• Manufacturer: Maxim

rent capabilities and degrade efficiency. Typically, a
22µH inductor is ideal for all operating conditions.
CCV, CCI, and CCS are the compensation points for the
three regulation loops. Bypass CCV with a 10kΩ resistor
in series with a 0.01µF capacitor to GND. Bypass CCI
and CCS with 0.01µF capacitors to GND. R7 and R13
serve as protection resistors to THM and CVS, respec-
tively. To achieve acceptable accuracy, R6 should be
10kΩ and 1% to match the internal battery thermistor.
In normal circuit operation with typical components, the
current-sense signals can have high-frequency tran-
sients that exceed 0.5V due to large current changes
and parasitic component inductance. To achieve prop-
er battery and input current compliance, the current-
sense input signals should be filtered to remove large
common-mode transients. The input current limit sens-
ing circuitry is the most sensitive case due to large cur-
rent steps in the input filter capacitors (C1 and C2) in
Figure 1. Use 1µF ceramic capacitors from CSSP and
CSSN to GND. Smaller 0.1µF ceramic capacitors can
be used on the CSIP and CSIN inputs to GND since the
current into the battery is continuous. Place these
capacitors next to the single-point ground directly
under the MAX1645/MAX1645A.
Bypass DCIN with a 1µF to GND (Figure 1). D4 protects
the device when the DC power source input is
reversed. A signal diode for D4 is adequate as DCIN
only powers the LDO and the internal reference.
Bypass LDO, BST, DLOV, and other pins as shown in
Figure 1.
Good PC board layout is required to achieve specified
noise, efficiency, and stable performance. The PC
board layout artist must be given explicit instructions,
preferably a pencil sketch showing the placement of
power-switching components and high-current routing.
Refer to the PC board layout in the MAX1645/
MAX1645A evaluation kit manual for examples. A
ground plane is essential for optimum performance. In
most applications, the circuit will be located on a multi-
layer board, and full use of the four or more copper lay-
ers is recommended. Use the top layer for high-current
connections, the bottom layer for quiet connections
(REF, CCV, CCI, CCS, DAC, DCIN, V
and the inner layers for an uninterrupted ground plane.
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
Battery Chargers with Input Current Limiting
Advanced Chemistry-Independent, Level 2
Current-Sense Input Filtering
______________________________________________________________________________________
Layout and Bypassing
Other Components
DD
, and GND),
2) Place the IC and signal components. Keep the main
3) Use a single-point star ground placed directly below
TRANSISTOR COUNT: 6996
switching nodes (LX nodes) away from sensitive ana-
log components (current-sense traces and REF
capacitor). Important: The IC must be no further
than 10mm from the current-sense resistors.
Keep the gate drive traces (DHI, DLO, and BST)
shorter than 20mm and route them away from the
current-sense lines and REF. Place ceramic bypass
capacitors close to the IC. The bulk capacitors can
be placed further away. Place the current-sense
input filter capacitors under the part, connected
directly to the GND pin.
the part. Connect the input ground trace, power
ground (subground plane), and normal ground to
this node.
• Minimize current-sense resistor trace lengths and
• Minimize ground trace lengths in the high-current
• Minimize other trace lengths in the high-current
ensure accurate current sensing with Kelvin con-
nections.
paths.
paths:
• Use > 5mm-wide traces
• Connect C1 and C2 to high-side MOSFET
• Connect rectifier diode cathode to low-side.
• LX node (MOSFETs, rectifier cathode, inductor:
(10mm max length)
MOSFET (5mm max length)
15mm max length). Ideally, surface-mount
power components are flush against one another
with their ground terminals almost touching.
These high-current grounds are then connected
to each other with a wide, filled zone of top-
layer copper so they do not go through vias.
The resulting top-layer subground plane is con-
nected to the normal inner-layer ground plane
at the output ground terminals, which ensures
that the IC’s analog ground is sensing at the
supply’s output terminals without interference
from IR drops and ground noise. Other high-
current paths should also be minimized, but
focusing primarily on short ground and current-
sense connections eliminates about 90% of all
PC board layout problems.
Chip Information
31