MAX5075 Maxim Integrated Products, MAX5075 Datasheet - Page 7

• Manufacturer Part Number: MAX5075
• Description: Push-Pull FET Driver
• Manufacturer: Maxim Integrated Products

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The power dissipation of the MAX5075 is a function of
the sum of the quiescent current and the output current
(either capacitive or resistive load). Maintain the sum of
the currents so the maximum power dissipation limit is
not exceeded. The power dissipation (P
quiescent switching supply current (I
culated as:
For capacitive loads, use the following equation to esti-
mate the power dissipation:
where C
NDRV2, V
MAX5075 NDRV_ switching frequency.
Calculate the total power dissipation (P
The MAX5075 sources and sinks large currents that can
create very fast rise and fall edges at the gate of the
switching MOSFETs. The high di/dt can cause unaccept-
able ringing if the trace lengths and impedances are not
well controlled. Use the following PC board layout guide-
lines when designing with the MAX5075:
•
Push-Pull FET Driver with Integrated Oscillator
Place one or more 0.1µF decoupling ceramic
capacitors from V
device as possible. Connect V
pins to large copper areas. Place one bulk capaci-
tor of 10µF on the PC board with a low-impedance
path to the V
LOAD
P
CC
LOAD
is the supply voltage, and f
is the capacitive load at NDRV1 and
CC
= 2 x C
P
P
_______________________________________________________________________________________
DISS
T
input and PGND of the MAX5075.
= P
Layout Recommendations
= V
LOAD
DISS
CC
CC
to PGND as close to the
+ P
x V
x I
Power Dissipation
LOAD
CCSW
CC
2
CC
CCSW
x f
T
NDRV_
DISS
) as follows:
and all ground
) can be cal-
NDRV_
) due to the
is the
•
•
TRANSISTOR COUNT: 1335
PROCESS: BiCMOS
Two AC current loops form between the device and
the gate of the driven MOSFETs. The MOSFETs
look like a large capacitance from gate to source
when the gate pulls low. The current loop is from
the MOSFET gate to NDRV1 and NDRV2 of the
MAX5075, to PGND, and to the source of the
MOSFET. When the gate of the MOSFET pulls high,
the current is from the V
pling capacitor, to V
and NDRV2, and to the MOSFET gate and source.
Both charging current and discharging current loops
are important. Minimize the physical distance and
the impedance in these AC current paths.
Keep the device as close to the MOSFET as possible.
TOP VIEW
and Clock Output
DGND
CLK
*EXPOSED PADDLE CONNECTED TO DGND.
I.C.
RT
1
2
3
4
CC
*EP
MAX5075
µMAX
Pin Configuration
of the MAX5075, to NDRV1
Chip Information
CC
terminal of the decou-
8
7
6
5
V
NDRV2
NDRV1
PGND
CC
7