AT94K ATMEL Corporation, AT94K Datasheet - Page 91

• Manufacturer Part Number: AT94K
• Description: 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
• Manufacturer: ATMEL Corporation

Timer/Counter 0 and 2
in PWM Mode
PWM Modes (Up/Down
and Overflow)
Rev. 1138F–FPSLI–06/02
The output compare registers are 8-bit read/write registers. The Timer/Counter Output Com-
pare Registers contains the data to be continuously compared with the Timer/Counter. Actions
on compare matches are specified in TCCR0 and TCCR2. A compare match does only occur
if the Timer/Counter counts to the OCR value. A software write that sets Timer/Counter and
Output Compare Register to the same value does not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock-cycle following the com-
pare event.
When PWM mode is selected, the Timer/Counter either wraps (overflows) when it reaches
$FF or it acts as an up/down counter.
If the up/down mode is selected, the Timer/Counter and the Output Compare Registers –
OCR0 or OCR2 form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on
the PE1(OC0/PWM0) or PE3(OC2/PWM2) pin.
If the overflow mode is selected, the Timer/Counter and the Output Compare Registers –
OCR0 or OCR2 form an 8-bit, free-running and glitch-free PWM, operating with twice the
speed of the up/down counting mode.
The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter
Control Registers – TCCR0 or TCCR2 respectively.
If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down
counter, counting up from $00 to $FF, where it turns and counts down again to zero before the
cycle is repeated. When the counter value matches the contents of the Output Compare Reg-
ister, the PE1(OC0/PWM0) or PE3(OC2/PWM2) pin is set or cleared according to the settings
of the COMn1/COMn0 bits in the Timer/Counter Control Registers TCCR0 or TCCR2.
If CTC0/CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start
counting from $00 after reaching $FF. The PE1(OC0/PWM0) or PE3(OC2/PWM2) pin will be
set or cleared according to the settings of COMn1/COMn0 on a Timer/Counter overflow or
when the counter value matches the contents of the Output Compare Register. Refer to Table
24 for details.
Table 24. Compare Mode Select in PWM Mode
Notes:
In PWM mode, the value to be written to the Output Compare Register is first transferred to a
temporary location, and then latched into the OCR when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchro-
nized OCR0 or OCR2 write. See Figure 52 and Figure 53 for examples.
CTCn
x
0
0
1
1
(2)
(1)
1. n = 0 or 2
2. x = don’ t care
COMn1
0
1
1
1
1
(1)
COMn0
x
1
1
0
1
(2)
(1)
Effect on Compare Pin
Not connected
Cleared on compare match, up-counting. Set
on compare match, down-counting (non-
inverted PWM)
Cleared on compare match, down-counting.
Set on compare match, up-counting (inverted
PWM)
Cleared on compare match,
set on overflow
Set on compare match, set on overflow
AT94K Series FPSLIC
f
f
f
f
Frequency
TCK0/2
TCK0/2
TCK0/2
TCK0/2
–
/510
/510
/256
/256
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