LPC2114 Philips Semiconductors (Acquired by NXP), LPC2114 Datasheet - Page 17

• Manufacturer Part Number: LPC2114
• Description: Single-chip 16/32-bit Microcontrollers; 128/256 KB Isp/iap Flash With 10-bit ADCthe LPC2114/LPC2124 Are Based on a 16/32 Bit ARM7TDMI-STM Cpu With Real-time Emulation And Embedded Trace Support, Together With 128/256 Kilobytes (kB) of Embedded High S
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 12805
Preliminary data
6.11.1 Features
6.12.1 Features
6.13.1 Features
6.12 UARTs
6.13 I
The LPC2114/LPC2124 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I
multi-master bus, it can be controlled by more than one bus master connected to it.
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C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
C implemented in LPC2114/LPC2124 supports bit rate up to 400 kbit/s (Fast I
C serial I/O controller
Measurement range of 0 V to 3 V.
Capable of performing more than 400,000 10-bit samples per second.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART1.
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
2
C bus may be used for test and diagnostic purposes.
2
C compliant bus interface.
Rev. 02 — 02 February 2004
Single-chip 16/32-bit microcontrollers
LPC2114/LPC2124
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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