MAX7369 Maxim Integrated Products, MAX7369 Datasheet - Page 14

• Manufacturer Part Number: MAX7369
• Description: (MAX7367 - MAX7369) 4-Channel I2C Switches / Multiplexer
• Manufacturer: Maxim Integrated Products

The MAX7367/MAX7368 feature an active-low RESET
input. When RESET is driven low for more than 4ns, the
MAX7367/MAX7368 reset the internal register and I
state machine to their default states, allowing a master
to recover from a bus fault condition.
When power is applied to V
holds the MAX7367/MAX7368/MAX7369 in a reset state
until V
the reset condition is released, and the MAX7367/
MAX7368/MAX7369 register and I
initialized to their default states (all zeroes), causing all
the channels to be deselected.
The MAX7367/MAX7368/MAX7369 can be used as a volt-
age translator from the main bus to the extended buses.
The output voltage (V
age (V
For the MAX7367/MAX7368/MAX7369 to be used as a
voltage translator, the V
than or equal to the lowest bus voltage.
The MAX7367/MAX7368/MAX7369 feature an I
patible, 2-wire serial interface consisting of a bidirec-
tional serial-data line (SDA) and a serial-clock line
(SCL). The master (typically a microcontroller) initiates
data transfer on the bus and generates the SCL.
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 9).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 10).
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (NA).
Both the master and the MAX7367/MAX7368/MAX7369
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related
clock pulse (ninth pulse) and keep it low during the
4-Channel I
14
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DD
DD
has reached the V
) (see the Typical Operation Characteristics ).
RESET Input (MAX7367/MAX7368)
PASS
PASS
) is limited by the supply volt-
Power-On Reset (POR)
2
POR
Start and Stop Conditions
DD
Voltage Translation
C Switches/Multiplexer
voltage should be lower
, internal POR circuitry
threshold. At this point,
2
C state machine are
Acknowledge Bit
I
2
C Interface
Bit Transfer
2
C-com-
2
C
high period of the clock pulse (Figure 11). In the case
of an unsuccessful data transfer, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Figure 9. Bit Transfer
Figure 10. Start and Stop Conditions
Figure 11. Acknowledge
SDA
SCL
SDA
SCL
CONDITION
CONDITION
SDA
SCL
START
START
S
DATA STABLE
DATA VALID
1
2
DATA ALLOWED
CHANGE OF
NOT ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGMENT
CLOCK PULSE FOR
8
9
CONDITION
STOP
P