MAX8751 Maxim Integrated Products, MAX8751 Datasheet - Page 10

• Manufacturer Part Number: MAX8751
• Description: Full-Bridge CCFL Inverter Controller
• Manufacturer: Maxim Integrated Products

Fixed-Frequency, Full-Bridge CCFL
Inverter Controller
10
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PIN
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
HSYNC
PGND2
LSYNC
DPWM
NAME
SHDN
CNTL
PSCK
HFCK
LFCK
BST2
TFLT
VFB
GL2
SEL
PS1
HF
LF
Transformer Secondary Voltage-Feedback Input. VFB pin sets secondary overvoltage limit by using a
capacitive voltage-divider between the high voltage of the CCFL lamp and GND. When the peak
voltage on VFB exceeds the internal overvoltage threshold, the controller turns on an internal current
sink, discharging the COMP capacitor, limiting the secondary voltage. See the Transformer
Secondary Voltage Limiting section for details.
Fault Timer-Adjustment Pin. A fault condition sets an internal current source to charge a capacitor
connected between TFLT and GND. Connect a capacitor from TFLT to GND to set the timeout period
for open-lamp fault and secondary short-circuit faults. See the Lamp-Out Protection section for
details.
Brightness Control Input. The usable brightness control range is from 0 to 2V. V
minimum brightness (10% DPWM duty cycle), V
duty cycle). When V
slave mode when CNTL is connected to V
Shutdown Control Input. The MAX8751 shuts down when SHDN is pulled to GND.
DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When
SEL is connected to V
Internal DPWM Oscillator Clock Output. LFCK becomes a logic-level input when CNTL is connected
to V
DPWM Signal Output. The DPWM output is used to control the DPWM frequency of the slave IC in
master-slave operation. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) section for details.
Phase-Shift Clock Output. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) and Phase Shift
(PS1, PS2) sections for details.
Main Switching Oscillator Clock Output. HFCK is a logic-level input when CNTL is connected to V
Main Switching Frequency Sync Input. Switching frequency can be synchronized with an external
signal on HSYNC.
Brightness Control Select Input. Brightness can be adjusted with an analog voltage on CNTL or with
an external sync signal. Connecting SEL to V
enable brightness control using external sync signal.
Frequency Adjustment Pin for Internal DPWM Oscillator. Connect a resistor from LF to GND to set the
internal DPWM oscillator frequency. f
when CNTL is connected to V
Frequency Adjustment Pin for Main Switching Oscillator. Connect a resistor from HF to GND to set the
main oscillator frequency. f
connected to V
Phase-Shift Select Input for Slave. For details, see the Slave Operation (HFCK, LFCK, PSCK, DPWM)
section.
Power Ground. PGND is the return for the GL2 gate driver.
Gate-Driver Output for Low-Side MOSFET NL2
High-Side Gate Driver GH2 Supply Input. The MAX8751 includes an integrated boost diode. Connect
a 0.1µF capacitor between LX2 and BST2 to complete the bootstrap circuit.
CC
.
CC
.
CNTL
CC
, the duty cycle of the LSYNC signal determines the brightness.
is between 2V and 3V, the brightness is still 100%. The MAX8751 enters into
SW
CC
= 54kHz × 100kΩ / R
. See the DPWM Dimming Control section for details.
DPWM
CC
= 208Hz × 150kΩ / R
. See the DPWM Dimming Control section for details.
CC
FUNCTION
CNTL
enables analog control input. Connect SEL to V
HF
= 2V represents full brightness (100% DPWM
. HF is a logic-level input when CNTL is
LF
. LF becomes a logic-level input
Pin Description
CNTL
= 0 represents
CC
CC
to
.