AL4CS241 AverLogic Technologies, Inc., AL4CS241 Datasheet - Page 7

• Manufacturer Part Number: AL4CS241
• Manufacturer: AverLogic Technologies, Inc.

7.0 Pin Definition and Description
Write Bus Signals
D[8:0]
/WEN1
WEN2
</LD>
WCLK
Read Bus Signals
Q[8:0]
/REN1
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
Symbol
The pin-out definition and function are described as following:
symbol
Pin
Pin
Data Outputs [21:12]
Write Enable 24
Write Enable 22
Read Enable 6
Write Clock 23
Data Inputs [26:32], 1,
Pin name
Pin name
2
Pin no.
Pin no.
TQFP
TQFP
[30:32],
[1:6]
28
26
27
[24:16]
10
Pin no.
Pin no.
PLCC
PLCC
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
Typ
I/O
I/O
typ
O
I
I
I
I
I
9-bit input data bus.
/WEN1 is the only Write Enable pin, if FIFO is
configured to support programmable flags.
When /WEN1 is LOW, data is written into the
FIFO on every rising edge of WCLK. If the
FIFO is configured to have two write enables,
/WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. When FIFO
is full (/FF = LOW), data will not be written
into FIFO.
The FIFO is configured at the Reset to either
have two write enables or support
programmable flags. If Write Enable 2<Load>
(WEN2</LD>) is HIGH at Reset (/RS =
LOW), this pin will operate as a second Write
Enable pin. If Write Enable 2<Load>
(WEN2</LD>) is LOW at Reset (/RS = LOW),
the FIFO is configured to support
programmable flags function and /WEN1 is the
only Write Enable pin.
Data is written into the FIFO on a rising edge of
WCLK when the Write Enable(s) are asserted.
Data will not be written into FIFO if /FF is not
LOW.
9-bit output data bus.
When both /REN1 and /REN2 are LOW, data is
read from the FIFO on every rising edge of
RCLK. Data will not be read from the FIFO if
the /EF is LOW.
Description
Description
December 14, 2001
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