KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet

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KSZ9021GN TR

Manufacturer Part Number
KSZ9021GN TR
Description
Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
Manufacturer
Micrel Inc
Datasheet
General Description
The KSZ9021GN is a completely integrated triple speed
(10Base-T/100Base-TX/1000Base-T) Ethernet Physical
Layer Transceiver for transmission and reception of data
on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9021GN provides the industry standard GMII/MII
(Gigabit Media Independent Interface / Media Independent
Interface) for connection to GMII/MII MACs in Gigabit
Ethernet Processors and Switches for data transfer at
1000 Mbps or 10/100Mbps speed.
The KSZ9021GN reduces board cost and simplifies board
layout by using on-chip termination resistors for the four
differential pairs and by integrating a LDO controller to
drive a low cost MOSFET to supply the 1.2V core.
The KSZ9021GN provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9021 I/Os and board.
Micrel LinkMD
identification of faulty copper cabling. Remote and local
loopback functions provide verification of analog and
digital data paths.
The KSZ9021GN is available in a 64-pin, lead-free QFN
package (See Ordering Information).
____________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
September 2010
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
®
TDR-based cable diagnostics permit
Features
• Single-chip 10/100/1000Mbps IEEE 802.3 compliant
• GMII/MII standard compliant interface
• Auto-negotiation to automatically select the highest link
• On-chip termination resistors for the differential pairs
• On-chip LDO controller to support single 3.3V supply
• Jumbo frame support up to 16KB
• 125MHz Reference Clock Output
• Programmable LED outputs for link, activity and speed
• Baseline Wander Correction
• LinkMD
• Parametric NAND Tree support for fault detection
• Loopback modes for diagnostics
• Automatic MDI/MDI-X crossover for detection and
408
Ethernet Transceiver
up speed (10/100/100Mbps) and duplex (half/full)
operation – requires only external FET to generate 1.2V
for the core
of faulty copper cabling
between chip I/Os and board.
correction of pair swap at all speeds of operation
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Gigabit Ethernet Transceiver
®
TDR-based cable diagnostics for identification
with GMII / MII Support
KSZ9021GN
M9999-091010-1.1

Related parts for KSZ9021GN TR

KSZ9021GN TR Summary of contents

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... The KSZ9021GN is available in a 64-pin, lead-free QFN package (See Ordering Information). ____________________________________________________________________________________________________________ Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( September 2010 KSZ9021GN Gigabit Ethernet Transceiver with GMII / MII Support Features • ...

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Micrel, Inc. More Features • Automatic detection and correction of pair swaps, pair skew and pair polarity • MDC/MDIO Management Interface for PHY register configuration • Interrupt pin option • Power down and power saving modes • Operating Voltages Core: ...

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Micrel, Inc. Revision History Revision Date Summary of Changes 1.0 10/13/09 Data sheet created 1.1 9/10/10 Added industrial temperature part number KSZ9021GNI. Added support for 2.5V VDD I/O. Added LED drive current. Corrected GMII receive timing for t Updated KSZ9021GN ...

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Micrel, Inc. Contents Pin Configuration ............................................................................................................................................................... 8 Pin Description ................................................................................................................................................................... 9 Strapping Options ............................................................................................................................................................ 14 Functional Overview ........................................................................................................................................................ 15 Functional Description: 10Base-T/100Base-TX Transceiver ...................................................................................... 16 100Base-TX Transmit.................................................................................................................................................... 16 100Base-TX Receive..................................................................................................................................................... 16 Scrambler/De-scrambler (100Base-TX only)................................................................................................................. 16 10Base-T Transmit ........................................................................................................................................................ 16 10Base-T ...

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Micrel, Inc. Absolute Maximum Ratings ............................................................................................................................................ 41 Operating Ratings ............................................................................................................................................................ 41 Electrical Characteristics ................................................................................................................................................ 41 Timing Diagrams .............................................................................................................................................................. 44 GMII Transmit Timing .................................................................................................................................................... 44 GMII Receive Timing ..................................................................................................................................................... 45 MII Transmit Timing ....................................................................................................................................................... 46 MII Receive Timing ........................................................................................................................................................ 47 Auto-Negotiation ...

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Micrel, Inc. List of Figures Figure 1. KSZ9021GN Block Diagram ..............................................................................................................................15 Figure 2. KSZ9021GN 1000Base-T Block Diagram – Single Channel.............................................................................17 Figure 3. Auto-Negotiation Flow Chart..............................................................................................................................20 Figure 4. KSZ9021GN GMII Interface...............................................................................................................................22 Figure 5. KSZ9021GN MII Interface .................................................................................................................................24 Figure 6. GMII Transmit ...

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Micrel, Inc. List of Tables Table 1. MDI / MDI-X Pin Mapping ................................................................................................................................... 18 Table 2. Auto-Negotiation Timers ..................................................................................................................................... 21 Table 3. GMII Signal Definition ......................................................................................................................................... 22 Table 4. MII Signal Definition ............................................................................................................................................ 24 Table 5. MII Management Frame Format ...

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Micrel, Inc. Pin Configuration September 2010 64-Pin QFN (Top View) 8 KSZ9021GN M9999-091010-1.1 ...

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Micrel, Inc. Pin Description Pin Number Pin Name 1 AVDDH 2 TXRXP_A 3 TXRXM_A 4 AVDDL 5 AVDDL TXRXP_B 8 TXRXM_B 9 AGNDH 10 TXRXP_C 11 TXRXM_C September 2010 (1) Type Pin Function P 3.3V analog V ...

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Micrel, Inc. Pin Number Pin Name 12 AVDDL 13 AVDDL 14 TXRXP_D 15 TXRXM_D 16 AVDDH 17 LED2 / PHYAD1 18 DVDDH 19 LED1 / PHYAD0 September 2010 (1) Type Pin Function P 1.2V analog 1.2V analog ...

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Micrel, Inc. Pin Number Pin Name 20 DVDDL 21 TXD0 22 TXD1 23 TXD2 24 TXD3 25 DVDDL 26 TXD4 27 TXD5 28 TXD6 29 TXD7 30 DVDDH 31 TX_ER 32 GTX_CLK September 2010 (1) Type Pin Function Single LED ...

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Micrel, Inc. Pin Number Pin Name 33 TX_EN 34 RXD7 35 RXD6 36 DVDDL 37 RXD5 38 RXD4 39 RXD3 / MODE3 40 DVDDH 41 RXD2 / MODE2 42 DVDDL 43 RXD1 / MODE1 44 RXD0 / MODE0 45 RX_DV ...

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Micrel, Inc. Pin Number Pin Name 51 MDIO 52 COL 53 INT_N 54 DVDDL 55 CLK125_NDO / LED_MODE 56 RESET_N 57 TX_CLK 58 LDO_O 59 AVDDL_PLL AVDDH 63 ISET 64 AGNDH PADDLE P_GND Note: 1. ...

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Micrel, Inc. Strapping Options Pin Number Pin Name Type 48 PHYAD2 17 PHYAD1 19 PHYAD0 39 MODE3 41 MODE2 43 MODE1 44 MODE0 45 CLK125_EN 55 LED_MODE Note: 1. I/O = Bi-directional. Pin strap-ins are latched during power-up or reset. ...

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Micrel, Inc. Functional Overview The KSZ9021GN is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer Transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable. Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 ...

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Micrel, Inc. Functional Description: 10Base-T/100Base-TX Transceiver 100Base-TX Transmit The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from ...

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Micrel, Inc. Functional Description: 1000Base-T Transceiver The 1000Base-T transceiver is based-on a mixed-signal / digital signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power efficient ...

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Micrel, Inc. Timing Recovery Circuit In 1000Base-T mode, the mixed-signal clock recovery circuit together with the digital phase locked loop is used to recover and track the incoming timing information from the received data. The digital phase locked loop has ...

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Micrel, Inc. Pair- Swap, Alignment, and Polarity Check In 1000Base-T mode, the KSZ9021GN • Detects incorrect channel order and automatically restore the pair order for the pairs (four channels) • Supports 50±10ns difference in propagation delay ...

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Micrel, Inc. For 1000Base-T mode, auto-negotiation is required and always used to establish a link. During 1000Base-T auto- negotiation, the Master and Slave configuration is first resolved between link partners, and then the link is established with the highest common ...

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Micrel, Inc. Auto-Negotiation Interval Timers Transmit Burst interval Transmit Pulse interval FLP detect minimum time FLP detect maximum time Receive minimum Burst interval Receive maximum Burst interval Data detect minimum interval Data detect maximum interval NLP test minimum interval NLP ...

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Micrel, Inc. GMII Signal Definition The following table describes the GMII signals. Refer to Clause 35 of the IEEE 802.3 Specification for more detailed information. GMII GMII Signal Name Signal Name (per spec) (per KSZ9021GN) GTX_CLK GTX_CLK TX_EN TX_EN TXD[7:0] ...

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Micrel, Inc. MII Interface The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface between MII PHYs and MACs, and has the following key characteristics: • Pin count is 16 pins (7 pins ...

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Micrel, Inc. MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. MII MII Signal Name Signal Name (per spec) (per KSZ9021GN) TX_CLK TX_CLK TX_EN TX_EN TXD[3:0] TXD[3:0] ...

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Micrel, Inc. MII Management (MIIM) Interface The KSZ9021GN supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/ Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021GN. An ...

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Micrel, Inc. Single LED Mode In Single LED Mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown in the following table. LED pin LED2 LED1 Tri-color Dual LED Mode In Tri-color ...

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Micrel, Inc. NAND Tree Support The KSZ9021GN provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree mode is enabled at power-up / reset with the MODE[3:0] strap-in pins set to 0100. The following ...

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Micrel, Inc. Power Management The KSZ9021GN offers the following power management modes: Power Saving Mode This mode is a KSZ9021GN green feature to reduce power consumption when the cable is unplugged effect when auto-negotiation mode is enabled ...

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Micrel, Inc. Register Map The IEEE 802.3 Specification provides a 32 register address space for the PHY. Registers 0 thru 15 are standard PHY registers, defined per the specification. Registers 16 thru 31 are vendor specific registers. The KSZ9021GN uses ...

Page 30

Micrel, Inc. Register Number (Hex) Description 27 (1Bh) Interrupt Control/Status 28 (1Ch) Digital Debug Control 1 29 (1Dh) – 30 (1Eh) Reserved 31 (1Fh) PHY Control Extended Registers 257 (101h) Strap Status 258 (102h) Operation Mode Strap Override 259 (103h) ...

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Micrel, Inc. Address Name Description 0.6 Speed Select [0.6, 0.13] (MSB) This bit is ignored if auto-negotiation is enabled (register 0.12 = 1). 0.5:0 Reserved Register 1 (1h) – Basic Status 1.15 100Base- capable 0 = Not ...

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Micrel, Inc. Address Name Description Register 3 (3h) – PHY Identifier 2 3.15:10 PHY ID Assigned to the 19th through 24 Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) 3.9:4 Model Number Six bit manufacturer’s model number ...

Page 33

Micrel, Inc. Address Name Description 5.11:10 Pause [5.11, 5.10] 5.9 100Base- capable capability 5.8 100Base- 100Mbps full-duplex capable Full-Duplex 100Mbps full-duplex capability 5.7 100Base- 100Mbps half-duplex ...

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Micrel, Inc. Address Name Description Register 8 (8h) – Auto-Negotiation Link Partner Next Page Ability 8.15 Next Page 1 = Additional Next Page(s) will follow 0 = Last page 8.14 Acknowledge 1 = Successful receipt of link word 0 = ...

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Micrel, Inc. Address Name Description 9.9 1000Base Advertise PHY is 1000Base-T full-duplex Full-Duplex 0 = Advertise PHY is not 1000Base-T full- 9.8 1000Base Advertise PHY is 1000Base-T half-duplex Half-Duplex 0 = Advertise PHY is not 1000Base-T ...

Page 36

Micrel, Inc. Address Name Description Register 12 (Ch) – Extended Register – Data Write 12.15:0 Extended 16-bit value to write to Extend Register Address Register – in register 11 (Bh) bits [7:0] write Register 13 (Dh) – Extended Register – ...

Page 37

Micrel, Inc. Address Name Description 17.2:1 Reserved 17.0 Reserved ® Register 18 (12h) – LinkMD – Cable Diagnostic 18.15 Reserved 18.14:8 Reserved 18.7:0 Reserved Register 19 (13h) – Digital PMA/PCS Status 19.15:3 Reserved 19.2 1000Base-T 1000 Base-T Link Status Link ...

Page 38

Micrel, Inc. Address Name Description 27.5 Page Receive 1 = Page Receive occurred Interrupt 0 = Page Receive did not occurred 27.4 Parallel Detect 1 = Parallel Detect Fault occurred Fault Interrupt 0 = Parallel Detect Fault did not occurred ...

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Micrel, Inc. Address Name Description 31.3 Duplex status Indicate chip duplex status 1 = Full-duplex 0 = Half-duplex 31.2 1000Base Indicate 1000Base-T Master mode Mater/Slave 0 = Indicate 1000Base-T Slave mode status 31.1 Software 1 = Reset chip, ...

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Micrel, Inc. Address Name Description Register 263 (107h) – Analog Test Register 263.15 LDO disable 1 = LDO controller disable 0 = LDO controller enable 263.14:9 Reserved 263.8 Low frequency 1 = Low frequency oscillator mode enable oscillator mode 0 ...

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Micrel, Inc. Absolute Maximum Ratings Supply Voltage (DVDDL, AVDDL, AVDDL_PLL)....... -0. (AVDDH) .......................................... -0. (DVDDH).......................................... -0. Input Voltage (all inputs) ........................ -0. Output Voltage (all outputs) ................... -0. Lead Temperature ...

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Micrel, Inc. Symbol Parameter Supply Current – Transceiver (equivalent to current draw through external transformer center taps for PHY transceivers with current-mode transmit drivers) I 3.3V for transceiver AVDDH CMOS Inputs V Input High Voltage IH V Input Low Voltage ...

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Micrel, Inc. Notes: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified ...

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Micrel, Inc. Timing Diagrams GMII Transmit Timing Timing Parameter 1000Base-T t cyc September 2010 Figure 6. GMII Transmit Timing – Data Input to PHY Description GTX_CLK period TX_EN, ...

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Micrel, Inc. GMII Receive Timing Timing Parameter 1000Base-T t cyc September 2010 Figure 7. GMII Receive Timing – Data Input to MAC Description RX_CLK period RX_DV, RXD[7:0], RX_ER ...

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Micrel, Inc. MII Transmit Timing Timing Parameter 10Base-T t cyc 100Base-TX t cyc September 2010 Figure 8. MII Transmit Timing – Data Input to ...

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Micrel, Inc. MII Receive Timing Timing Parameter 10Base-T t cyc 100Base-TX t cyc September 2010 Figure 9. MII Receive Timing – Data Input to ...

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Micrel, Inc. Auto-Negotiation Timing ...

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Micrel, Inc. MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising ...

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Micrel, Inc. Reset Timing The recommended KSZ9021GN power-up reset timing is summarized in the following figure and table. Parameter t sr After the de-assertion of reset recommended to wait a minimum of 100µs before starting programming on the ...

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Micrel, Inc. The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ9021GN device. The RST_OUT_N ...

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Micrel, Inc. Reference Clock – Connection and Selection A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9021GN. The reference clock is 25 MHz for all operating modes of the ...

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Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished ...

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