STK12C68-M Simtek, STK12C68-M Datasheet

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STK12C68-M

Manufacturer Part Number
STK12C68-M
Description
CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM
Manufacturer
Simtek
Datasheet
www.DataSheet4U.com
LOGIC BLOCK DIAGRAM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
FEATURES
• 40, 45 and 55ns Access Times
• 15 mA I
• Automatic
• Hardware or Software initiated
• Automatic
• 100,000
• 10 year data retention in
• Automatic
• Software initiated
• Unlimited
• Single 5V 10% Operation
• Available in multiple standard packages
A
A
A
A
A
A
A
A
12
0
1
2
3
4
5
6
7
3
4
5
6
7
8
9
EEPROM
CC
STORE
RECALL
at 200ns Access Speed
STORE
STORE
RECALL
cycles to
A
0
Timing
RECALL
cycles from
to
COLUMN DECODER
on Power Up
A
STATIC RAM
1
COLUMN I/O
256 x 256
EEPROM
ARRAY
A
2
EEPROM
EEPROM
EEPROM ARRAY
A
from
10
256 x 256
A
on Power Down
11
EEPROM
STORE
RECALL
EEPROM
STORE
MIL-STD-883 / SMD # 5962-94599
to
CONTROL
A
STORE/
RECALL
0
4-53
A
12
DESCRIPTION
The Simtek STK12C68-M is a fast static RAM (40, 45
and 55ns), with a nonvolatile EEPROM element incor-
porated in each static memory cell. The SRAM can be
read and written an unlimited number of times, while
independent nonvolatile data resides in EEPROM.
Data transfers from the SRAM to the EEPROM (the
STORE operation) take place automatically upon power
down using charge stored in an external 100
capacitor. Transfers from the EEPROM to the SRAM
(the RECALL operation) take place automatically on
power up. Software sequences may also be used to
initiate both STORE and RECALL operations.
STORE can also be initiated via a single pin.
The STK12C68-M is available in the following pack-
ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC.
Nonvolatile Static RAM
HSB
W
G
E
DQ
DQ
A
A
A
A
A
A
A
8K x 8 AutoStore™
6
5
4
3
2
1
0
0
1
PIN CONFIGURATIONS
10
11
12
4
5
6
7
8
9
13
3
STK12C68-M
TOP VIEW
28 - LCC
14
2
15
1
A
W
DQ
E
G
V
V
V
HSB
CMOS nvSRAM
0
CCX
SS
CAP
28 27
16
- A
0
17
- DQ
26
25
24
23
22
21
20
19
18
12
PIN NAMES
HSB
A
A
A
G
DQ
DQ
7
A
E
11
8
9
10
7
6
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
Capacitor
Hardware Store/Busy
DQ
DQ
DQ
V
V
CAP
A
A
A
A
A
A
A
A
A
SS
12
7
6
5
4
3
2
1
0
0
1
2
28 - 300 C-DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STK12C68-M
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
W
HSB
A
A
A
G
A
DQ
DQ
DQ
DQ
DQ
E
CCX
11
8
9
10
7
6
5
4
3
A
F

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STK12C68-M Summary of contents

Page 1

... MIL-STD-883 / SMD # 5962-94599 DESCRIPTION The Simtek STK12C68 fast static RAM (40, 45 and 55ns), with a nonvolatile EEPROM element incor- porated in each static memory cell. The SRAM can Power Down EEPROM read and written an unlimited number of times, while to independent nonvolatile data resides in EEPROM ...

Page 2

... STK12C68-M ABSOLUTE MAXIMUM RATINGS Voltage on typical input relative –0.6V to 7.0V SS Voltage on DQ and .–0. 0-7 Temperature under bias . . . . . . . . . . . . . . . . . . . . . . – 125 C Storage temperature – 150 C Power dissipation .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA (One output at a time, one second duration) DC CHARACTERISTICS ...

Page 3

... STK12C68-40M PARAMETER MIN AVAV 3 t AVQV 5 t AXQX 2 t AVAV 1 t ELQV 6 t ELQX 4 t GLQV 8 t GLQX 4-55 STK12C68 5.0V 10%) CC STK12C68-45M STK12C68-55M UNITS MAX MIN MAX MIN MAX ...

Page 4

... STK12C68-M WRITE CYCLES #1 & #2 SYMBOLS NO. PARAMETER #1 #2 Alt Write Cycle Time AVAV AVAV Write Pulse Width WLWH WLEH Chip Enable to End of Write ELWH ELEH Data Set-up to End of Write DVWH DVEH Data Hold After End of Write ...

Page 5

... These parameters guaranteed but not tested. Note n: HSB is an I/O that has a weak internal pullup basically an open drain output meant to allow STK12C68- ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins. ...

Page 6

... STORE or RECALL will still be initiated. Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a STORE or RECALL . Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles ...

Page 7

... The STK12C68-M has two separate modes of opera- tion: mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static . In nonvolatile mode, data is transferred from RAM to (the operation) or from STORE SRAM EEPROM to (the operation). In this mode RECALL EEPROM SRAM functions are disabled. ...

Page 8

... V CALL again rises above V . SWITCH If the STK12C68 WRITE state at the end of power-up RECALL , the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected between W and system V HARDWARE PROTECT The STK12C68-M offers hardware protection against ...

Page 9

... SWITCH to pull HSB ; if HSB doesn't actually get below V LOW the part will stop trying to pull HSB AutoStore ™attempt. LOW AVERAGE ACTIVE POWER The STK12C68-M has been designed to draw signifi- cantly less power when E is (chip enabled) but the LOW V V CAP ...

Page 10

... STK12C68-M STK12C68 - 5962-94599 ORDERING INFORMATION Temperature Range M = Military (-55 to 125 degrees C) Access Time 40 = 40ns 45 = 45ns 55 = 55ns Package C = Ceramic 28 pin 300-mil DIP with gold lead finish K = Ceramic 28 pin 300-mil DIP with solder DIP finish L = Ceramic 28 pin LCC Retention / Endurance ...

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