Q2686 Wavecom, Q2686 Datasheet - Page 33

• Manufacturer Part Number: Q2686
• Description: Wireless CPU
• Manufacturer: Wavecom

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3.4.2 I2C Bus
The I2C interface includes a clock signal (SCL) and data signal (SDA) complying
with a 100Kbit/s-standard interface (standard mode: s-mode).
The I²C bus is always master.
The maximum speed transfer range is 400Kbit/s (fast mode: f-mode).
For more information on the bus, see the “I²C Bus Specification Version 2.0”
from PHILIPS [13].
3.4.2.1
I²C bus waveform in master mode configuration:
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q2686_PTS_001-007
SCL
SDA
I²C Waveforms
T-
free
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confidential ©
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Figure 4: I²C Timing diagrams, Master
Data valid
T-
high
T-
hold
SCL
data-
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freq
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setup
data-
Data valid
Q2686 Wireless CPU
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Interfaces
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March 6, 2007
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