MTC20136 ST Microelectronics, Inc., MTC20136 Datasheet
MTC20136
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MTC20136 Summary of contents
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... MTC20136PQ- l1 MTC20136MB-I1 Can also be ordered using kit number MTK20131 or MTC20455 DESCRIPTION The MTC20136 is a dedicated controller chip, spe- cifically designed to control operations of the ST- Microelectronics MTC20136 offers direct glueless interfaces to the MTC20135 and MTC20455 DMT/ATM transciever and implements a complete control interface for parameters and commands exchange between transceiver and system management ...
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... MTC20136 Functional Description Figure 1 is showing the global block diagram of the MTC20136. The functions can be grouped into the following: – Microcontroller – External Bus Interface – Control Interface (CTRLE) – Peripherals – Miscellaneous Microcontroller The microcontroller block includes an ARM-based microcore and its associated internal memory. 16 Kbytes on internal RAM and 128 x 32-bit words of ROM are foreseen ...
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... E_A[19:16] E_A[15:0] E_D[15:0] C_clk C_A[8:0] C_notCS C_Mode[1:0] C_notWr C_notRd TROM EIT[3:0] CLK_E RESETN RSRXD2 RSTXD2 JTAG Interface Test Interface EBI Interface CTRL-E Interface Misc Peripherals MTC20136 TDO T_ACK E_CLK E_ALE E_nRDY E_nWEO E_nWE1 C_D[7:0] C_notint C_notRdy Boot_M[1:0] RSRXD1 RSTXD1 PA1 PA0 3/25 ...
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... Chip select signal (ASIC 2) O Chip select signal (ASIC 3) O Chip select signal (ASIC 4) I Data acknowledge O Output enable O Write enable LSB / W/notR indication O Write enable MSB I MTC20136 Master clock I/O Port A bit[0] I/O Port A bit[1] O Serial TX port I Serial RX port O Serial TX port I Serial RX port I ...
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... EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address External Interrupt External Interrupt VDD VSS External Interrupt External Interrupt In -3 Tracking ICE Mode Select (0) EBI Clock Out EBI ALE VDD MTC20136 Description Function 5/25 ...
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... MTC20136 PQFP144 Pin Configuration (continued) (Default Value between ( )) Pin# Name 19 VSS 20 E_nRDYRCV 21 E_nWE0 22 E_nWE1 23 E_notCS_4 24 VDD 25 VSS 26 Boot_M0 27 Boot_M1 28 PA0 29 PA1 30 TROM 31 VDD 32 VSS 33 T_REQA 34 T_REQB 35 T_ACK 36 IDDQ 37 RESETN 38 TDI 39 TDO 40 VDD 41 VSS 42 TMS 43 nTRST 44 TCK 45 RSTXD1 46 RSRXD1 47 RSTXD2 48 VDD 49 VSS ...
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... CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS Reserved (0) Reserved (0) EBI - ASIC Chip Select EBI - ASIC Chip Select EBI - ASIC Chip Select VDD VSS EBI - SDRAM Chip Select EBI - SRAM Chip Select EBI - FLASH Chip Select EBI - OE MTC20136 Function 7/25 ...
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... MTC20136 PQFP144 Pin Configuration (continued) (Default Value between ( )) Pin# Name 103 E_D15 104 VDD 105 VSS 106 E_D14 107 E_D13 108 E_D12 109 E_D11 110 E_D10 111 E_D9 112 VSS 113 VDD 114 E_D8 115 E_D7 116 E_D6 117 E_D5 118 ...
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... VSS BootMode Select BootMode Select General Purpose IO General Purpose IO Boot Mode Select VDD VSS Reserved for test (0) Reserved for test (0) Reserved for test Reserved for test (0) RESET (Active Low) JTAG Interface JTAG Interface VDD VSS JTAG Interface JTAG Interface MTC20136 Function 9/25 ...
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... MTC20136 LFBGA160 Pin Configuration (continued) Pin# Name N5 TCK L5 RSTXD1 P5 RSRXD1 M6 RSTXD2 N6 VDD P6 VSS L6 RSRXD2 N7 TESTSE P7 SCAN_CLK M7 C_nInt L7 VDD P8 VSS N8 CLK_IN M8 VSS L8 C_nRdy N9 C_nRd M9 VDD P10 VSS N10 C_nWr L9 C_Mode0 P11 C_Mode1 M10 C_notCS N11 C_CLK P12 VDD L10 VSS N12 C_D0 ...
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... EBI Data EBI Data EBI Data EBI Data EBI Data EBI Data VSS VDD EBI Data EBI Data EBI Data EBI Data EBI Data VDD VSS EBI Data EBI Data EBI Data EBI Data EBI Address VDD VSS EBI Address MTC20136 Function 11/25 ...
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... MTC20136 LFBGA160 Pin Configuration (continued) Pin# Name B7 E_A2 A7 E_A3 C7 E_A4 D6 VDD A6 VSS B6 E_A5 C6 E_A6 A4 E_A7 D5 E_A8 B5 E_A9 A3 VDD C5 VSS B4 E_A10 A2 E_A11 B3 E_A12 B1 E_A13 External pins E_D[15:0] 16 bit data, multiplexed address/data E_A[19:0] 20 bit address (including commands for SDRAM) nCS[7:4] external chip select ...
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... If the TROM external pin is high at reset, the MTC20136 boots from an external FEPROM. c) Internal boot mode: If the TROM external pin is low at reset, the MTC20136 boots from its internal ROM. This mode can be used to perform code download from a host. Boot modes are used at RESET time. ...
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... MTC20136 Figure 3. Access to MTC20135, MTC20455 E_CLK notCSi ALE E_D notRDYRCV W/notR SDRAM The SDRAM interface allows a glue-less interconnection of 1 SDRAM. Following features are provided for SDRAM access. – 16 bit databus and 12 bit address bus. – control signals : S_nCS, S_nRAS, S_nCAS, S_nWE, S_DQM[1:0 Control signal timing All SDRAM actions are triggered at the rising edge of its clock ...
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... E_nCS[0:1], E_nOE, E_nWE0, E_nWE1 – setup and wait state insertion – and 32 bit access by MTC20136 bit memory according to little endian convention Figure 6. EBI memory access (32-bit Word R bit memory), maximum speed timing E_nCSi ...
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... CTRLE The Ctrl-E interface is an ADSL-oriented mailbox system to exchange control and status messages be- tween MTC20136 and an external controller. It consists of a mailbox and a physical interface. The mailbox has two 8-bit command registers to pass commands from the MTC20136 internal controller bus (ASB) to Ctrl-E (RxCommand) and from Ctrl-E to ASB (TxCommand), and two status registers (RxComAv and Tx- ComAv) to indicate the status of the command register ...
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... MTC20136 Initial Function 00 Command written by Ctrl-E, read by h ASB 00 Command written by ASB, read by h Ctrl-E 0 1-bit register : command b available 0 1-bit register : command b available 00 Semaphore for access to written by ...
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... MTC20136 Ctrl-E Semaphore A simple semaphore mechanism is provided to allow control of the data consistency of the Ctrle- DataBuffer. One mailbox address is defined as a two-bit semaphore register protected by control logic to prevent unallowed write accesses to this register. Before the databuffer is read or written by one of the two interfaces (ASB or Ctrl-E) this interface should perform a ’ ...
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... Bus cycle ready indication, indicates that data on bus can be sampled or removed, same as in mode MTC20136 PIN C_A[8:0] C_D[7:0] C_notCS C_notInt C_Mode[1:0] C_notWr C_notRd C_notRdy C_Mode[1:0] C_notWr C_notRd C_notRdy ...
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... MTC20136 Table 8. write cycle timing in parallel modes 0 and 1 Symbol t1 C_A Setup to C_notDS (C_notWr) low t2 C_notCS, C_Rd/notWr setup to C_notDS (C_notWr) low t3 C_notDS (C_notWr) pulse width t4 C_D setup to C_notDS (C_notWr) high t5 C_A, C_D hold from C_notDS (C_notWr) high t6 C_notDtAck (C_notRdy) valid from C_notDS (C_notWr) low ...
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... Four pins are available for general purpose IOs, two are used as inputs to specify the boot configuration and two are output under SW control. The latter can be used for instance to drive external LEDs. Reset The MTC20136 has an asynchronous, active-low reset pin. An external clock is required to leave the reset state. Clock The MTC20136 is operated from the 35 ...
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... MTC20136 Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/ or outputs unless specified oth- erwise. Table 12. CMOS IO buffers generic characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device ...
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... D1 D3 108 109 144 1 e inch MECHANICAL DATA TYP. MAX. 0.160 0.135 0.144 0.015 0.009 1.228 1.238 1.102 1.106 0.896 0.026 1.228 1.238 1.102 1.106 0.896 0.031 0.037 0.063 PQFP144 MTC20136 OUTLINE AND PQFP144 0.10mm .004 Seating Plane C K 23/25 ...
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... MTC20136 mm DIM. MIN. TYP. MAX. A 1.210 1.700 0.047 A1 0.270 0.010 A2 1.120 b 0.450 0.500 0.550 0.018 D 11.85 12.00 12.15 0.466 D1 10.40 E 11.85 12.00 12.15 0.466 E1 10.40 e 0.720 0.800 0.880 0.028 f 0.650 0.800 0.950 0.025 ddd 0.120 24/25 inch MIN. TYP. MAX. 0.067 0.044 0.02 0.021 0.472 0.478 0.409 0.472 0.478 Body ...
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