MTC20454 ST Microelectronics, Inc., MTC20454 Datasheet
MTC20454
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MTC20454 Summary of contents
Page 1
... ADSL Front-end for high density, low power central office and digital loop carrier equipment DESCRIPTION ■ The MTC20454 is the first DynaMiTe ADSL (Asyn- chronous Digital Subscriber Line) analog front end designed specifically for the central office Figure 1. Sample board layout ...
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... MTC20454 PIN DESCRIPTION N° Pin Digital Interface 1 DVSS Negative supply for input IOs + core 2 TX7 Transmit data bus bit 7 (MSB) 3 TX6 Transmit data bus bit 6 4 TX5 Transmit data bus bit 5 5 TX4 Transmit data bus bit 4 6 TX3 Transmit data bus bit 3 ...
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... TX driver Ana supply TX driver Ana supply Ana supply TX driver Ana supply Ana supply Board Board Ana supply Board Board Test Test Test Test MTC20454 Type VSSI OANA OANA VDDI OANA OANA VSSI OANA OANA VDDI OANA OANA VSSI OANA OANA VDDI ...
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... MTC20454 Figure 2. MTC20454 Grounding and Decoupling Networks Analog VDD 100nF Figure 3. PIN CONNECTION VREF 28 VRAN 29 VRAP 30 31 DACVREF 32 33 L3GP0 34 A VDDDAC 35 36 L3GP1 37 L2GP0 38 L2GP1 39 A VSSDAC 40 VSSDS A 41 L3DR VSD 42 VDDDS VDDTXDR V 44 L3DR VSSTXDR V 46 ...
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... Hard driven outputs: RXi, CLKWD, LiGPi, LiDRVi, LiDRVSD Clock Driver Output Symbol Parameters V Low level output voltage OL V High level output voltage OH C Load capacitance load Parameter Description Parameter Description Test Condition Test Cond Iout = 4 mA Iout = 4 mA MTC20454 Min Max -0.5 5 -0.5 VDD + 0.5 -40 125 300 100 Min Max 3.0 3.6 2.7 3 ...
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... V supply and is packaged in a 100 pins TQFP in order to reduce PCB area. The following descriptions apply to each of the four analog front ends in the chip: The Receiver (RX) The DMT signal coming from the lines to the MTCMTC20454MTC2045420454 is first filtered by the two following external filters: ■ POTS HP filter: Attenuation of speech and POTS signalling. ...
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... L0AACrx + - 276kHz AAF DAC 1.1 mHz HCDS + - - + L1AGCrx L2AGCrx - + - L1AACrx + - L2AACrx + 276kHz 276kHz AAF AAF ADC Digital ifce DAC 1.1 mHz 1.1 mHz HCDS HCDS + - + L0AGCtx L1AGCtx - + - L3AGCrx + - + - L3AACrx + - 276kHz AAF Tuning circuit L/V - Ref CTRL/TST ifce DAC DAC 1.1 mHz HCDS - + - L2AGCtx L3AGCtx + - + MTC20454 7/15 ...
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... In fact also used to internally fix the LNA input common mode voltage at the nominal value: AVDD/2. This is done by the use of an internal biasing circuit therefore mandatory to de-couple the MTC20454 input from any external DC biasing system. The Low Noise Amplifier (LNA) placed after the ATT will be used in combination with the attenuation block. The goal is to obtain a range of RX path input level varying from – ...
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... The noise on the power supplies for the TX-path must be lower than the following: ■ < 50 mVrms in band white noise for AVDD. ■ < 15 mVrms in band white noise for Pre-driver AVDD. Figure 6. Power Supply Rejection TX Pre-driver Capability dB -40 -50 -60 -70 1k 10k 100k1M 10M MTC20454 Hz 9/15 ...
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... DIGITAL INTERFACE Control Interface The digital code setting for the MTC20454 configuration is sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (‘0’), the three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched but they are overruled by the normal settings if the TEST pin is low ...
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... RX2/TX2 RX3/TX3 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 MTC20454 Word bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit n.u n ...
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... Th Tdv Reset Function The MTC20454 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The chip status is depicted in the following table: CLKM pin is replicating the CLKIN input clock. System clock available CLKWD is not generated. The pin stays at high level ...
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... Test is enabled with a high level n the TEST pin. The actual value of TX1 and TX0 bits on the rising edge of the TEST pin will set the test mode. The available test modes and their corresponding signal values are summarized in the following table: Table 6. Tests mode accessMTC20454 TX1 TX0 ...
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... MTC20454 mm DIM. MIN. TYP. MAX. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.007 C 0.09 0.20 0.003 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 L 0.45 0.60 0.75 0.018 L1 1.00 K 0˚ (min.), 3.5˚ (typ.), 7˚(max.) ccc 0.080 14/15 inch MIN. TYP. MAX. 0.063 0.006 0.055 0.057 0.009 0.011 0.008 0.630 0.551 0.472 0.020 0.630 0.551 ...
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