MTC20455 ST Microelectronics, Inc., MTC20455 Datasheet
MTC20455
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MTC20455 Summary of contents
Page 1
... ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed-Solomon error corrections, with and without interleaving. The MTC20455 is controlled and configured by the MTC20136 Transceiver Controller. All program- mable coefficients and parameters are loaded by the Controller. The MTC20136 also controls the initialisation procedure and performs the monitor- ing and adaptive functions during operation ...
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... INTB_2 37 INTB_3 38 TEST RESETB 39 VSS 40 Table 1. I/O types Type I I-PD I- 2/23 MTC20455 (PQFP160) UTOPIA RX Function Input Input with internal pull down resistor Input with internal pull up resistor Output Tri-state output Bidirectional Ground Power 120 VDD 119 AFTXD_2_3 AFE_0 118 AFTXD_2_2 117 ...
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... Processor Clock TLCHT_TC Address bit 1 TLCHT_TC Address Latch TLCHT_TC Chip select line 0 VSS+1.8V TLCHT_TC Chip select line 1 TLCHT_TC Chip select line 2 TLCHT_TC Chip select line 3 TLCHT_TC Write/Not read BD4STARP_TC Ready indication TLCHTDQ_TC I960/Generic selection BD4STARP_TC Requests OBC interrupt service line 0 MTC20455 Description 3/23 ...
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... TLCHT_TC Utopia receive address TLCHT_TC Utopia receive address TLCHT_TC Utopia receive address BD4STARP_TC MTC20455 Reset line 0 BD4STARP_TC MTC20455 power down line 0 TLCHT_TC Receive data nibble line 0 TLCHT_TC Receive data nibble line 0 TLCHT_TC Receive data nibble line 0 TLCHT_TC Receive data nibble line 0 ...
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... Transmit data nibble line 0 BD4STARP_TC Transmit data nibble line 0 BD4STARP_TC Transmit data nibble line 0 VSSIO+3.3V BD4STARP_TC MTC20455 Reset line 1 BD4STARP_TC MTC20455 power down line 1 TLCHT_TC Receive data nibble line 1 TLCHT_TC Receive data nibble line 1 TLCHT_TC Receive data nibble line 1 TLCHT_TC Receive data nibble line 1 VSS+1 ...
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... I 159 U_TXREFB I 160 VDD P 6/23 Technology BD4STARP_TC MTC20455 Reset line 3 BD4STARP_TC MTC20455 power down line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 VSS+1.8V TLCHT_TC Start of word indication line 3 TLCHT_TC ...
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... MCLK_0 AFTXD_0_0 AFRXD_0_3 CLWD_0 VDD_15 Description Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus VSSIO+3.3V Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus MTC20455 14 A AFRESET_3 B VDD_2 C VSS_1 D VDD_1 E AFRXD_2_1 F AFRESET_2 G AFTXD_1_2 H VSS_17 J ...
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... MTC20455 Table 4. LFBGA 160 pin list (continued) Signal Pin # Signal Name type F4 VDD P F1 AD_12 B G2 AD_13 B G3 AD_14 B G4 AD_15 B G1 VSS G H2 PCLK ALE I J2 CSB_0 I H4 VDD P J3 CSB_1 I J1 CSB_2 I K2 CSB_3 I J4 WR_RDB I K3 ...
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... Transmit data nibble line 2 BD4STARP_TC Transmit data nibble line 2 BD4STARP_TC Transmit data nibble line 2 VSS+1.8V BD4STARP_TC MTC20455 Reset line 3 BD4STARP_TC MTC20455 power down line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 TLCHT_TC Receive data nibble line 3 VSS+1 ...
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... MTC20455 Table 4. LFBGA 160 pin list (continued) Signal Pin # Signal Name type C5 U_TXDATA_3 I A3 U_TXDATA_4 I B4 U_TXDATA_5 I C4 U_TXDATA_6 I B3 U-TXDATA_7 I B2 U_TXREFB I A2 VDD P ELECTRICAL SPECIFICATIONS GENERIC The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. ...
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... SCHMITT IOUT = XMa* IOUT = -Xma* 0.85*vDD Test Conditions Min 2.0 0.9 slow edge < 1V/µs 1.3 slow edge <1V/µs 0.4 IOUT = XMa* IOUT = -Xma* 2.4 Test Conditions Min 3.0 1.62 -40 MTC20455 Typ Max Unit 0.2*VDD 0 Typ Max Unit 0 1.35 V 1.9 V 0.7 V ...
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... MTC20455 Functional Description Fig.4 shows the global block diagram of the MTC20455. The functions can be grouped into the following: ■ DMT modems ■ Quad or single AFE interface ■ Utopia interface ■ Controller interface ■ Miscellaneous DMT Modem Description The following section essentially describes the sequence of actions for the receive direction, correspond- ing functions for the transmit direction are readily derived ...
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... A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. FFT FEQ Rotor FEQ Coefficients FEQ Update MTC20455 Trellis coding Demapper Monitor Monitor Indications 13/23 ...
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... MTC20455 Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T1.413. Ad- ditions described in the Issue 2 of this specification are also supported. The data received from the demap- per is split into two paths, one dedicated to an interleaved data flow, the other one for a non-interleaved data flow ...
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... AFRXD_i[0] AFRXD_i[1] AFRXD_i[2] AFRXD_i[3] GP_IN FAST Cell Descrambler HEC Synchronizer Cell Descrambler HEC Synchronizer SLOW Cycle 0 Cycle MTC20455 BER Cell filter To Interface Module Cell filter BER Cycle 2 Cycle 3 b8 b12 b9 b13 b10 b14 b11 b15 t2 t3 15/23 ...
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... MTC20455 Table 11. Bits assigned to pins/time slot for muxed-line interface 0 1 Cycles line 0 AFRXD_1[ AFRXD_1[ AFRXD_1[ AFRXD_1[ Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals result 4 cycles are needed to trans- fer 1 word. Refer to Table 11 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal ...
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... Min Typ Max 35.328 28 Min Typ Max 16 4 Min Typ Max 20 4 MTC20455 7 line b10 b11 b12 b13 b14 b15 Unit MHz ns % Unit ns ns Unit ns ns 17/23 ...
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... MTC20455 Table 17. AFRXD AC Electrical Characteristics AC Electrical Characteristics for AFRXD Symbol Parameter Ts Data setup time Th Data setup time Digital Interface With a Utopia Level 2 Interface the ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM direction is referred to as the receive direction ...
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... TxClav and 1 RxClav.» PHY Device Identification The MTC20455 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the Utopia PHY address register ...
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... MTC20455 Figure 13. Address and ALE timing diagram ALE Tavs AD [15:0] Table 20. Data input with respect to clock Symbol Tdh Data write hold time Tds Data write setup time Table 21. Data output with respect to clock Symbol Tzd Data active delay from clock data ...
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... D 30.95 31.20 31.45 1.219 D1 27.90 28.00 28.10 1.098 D3 25.35 e 0.65 E 30.95 31.20 31.45 1.219 E1 27.90 28.00 28.10 1.098 E3 25.35 L 0.65 0.80 0.95 0.026 L1 1.60 0°(min.), 7°(max.) K inch TYP. MAX. MECHANICAL DATA 0.160 0.135 0.144 0.015 0.009 1.228 1.238 1.102 1.106 0.998 0.026 1.228 1.238 1.102 1.106 0.998 0.031 0.037 0.063 MTC20455 OUTLINE AND PQFP160 21/23 ...
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... MTC20455 mm DIM. MIN. TYP. MAX. A 1.210 1.700 0.047 A1 0.270 0.010 A2 1.120 b 0.450 0.500 0.550 0.018 D 11.85 12.00 12.15 0.466 D1 10.40 E 11.85 12.00 12.15 0.466 E1 10.40 e 0.720 0.800 0.880 0.028 f 0.650 0.800 0.950 0.025 ddd 0.120 22/23 inch MIN. TYP. MAX. 0.067 0.044 0.02 0.021 0.472 0.478 0.409 0.472 0.478 Body ...
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