TSS461F ATMEL Corporation, TSS461F Datasheet - Page 27

• Manufacturer Part Number: TSS461F
• Description: VAN Data Link Controller
• Manufacturer: ATMEL Corporation

Ma, Mb: Operating
mode command bits
ETIP: Enable
Transmission In
Progress
ESDC: Enable System
Diagnosis Clock
Command Register
(0x03)
GRES: General Reset
SLEEP: Sleep
Command
7615A–AUTO–02/06
Table 7. Diagnosis System Command Bits
One: Enable TIP generation
Zero: Disable TIP generation.
•
One: Enable SDC divider.
Zero: Disable SDC divider.
-The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis.
•
•
•
The Reset circuit command bit performs, if set, exactly as if the external reset pin was asserted.
This command bit has its own auto-reset circuitry.
One: Reset active
Zero: Reset inactive
If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode,
all non-user registers are setup to minimize power consumption and the oscillator is stopped. To
exit from this mode, the user must set either the idle or activate commands.
One: Sleep active
Zero: Sleep inactive
The Transmission In Progress (TIP) tells the diagnostic system to enable transmission
diagnosis.
Write only register.
Reserved: Bit 1, 2 these bit cannot be set by the user; a zero must always be written to
these bit.
If the circuit is operating at low bit rates there might be a considerable delay between the
writing of this register and the performing of the actual command (worst case 6 timeslots).
The user must verify, by reading the Line Status Register (0x04) that the commands have
been performed.
GRES
7
Ma
0
0
1
1
SLEEP
6
IDLE
5
Mb
0
1
0
1
ACTI
4
Forces the Communication on RxD0 (differential)
Forces the Communication on RxD2 (DATA)
Forces the Communication on RxD1 (DATA)
Automatic selection
REAR
3
2
0
TSS461F
1
0
MSDC
0
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