PIC16C65A Microchip Technology, PIC16C65A Datasheet - Page 78

• Manufacturer Part Number: PIC16C65A
• Description: 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C6X
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
10.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 10-2). An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
DS30234D-page 78
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
U-0
—
Capture Mode
CCP PIN CONFIGURATION
If the RC2/CCP1 pin is configured as an
output, a write to PORTC can cause a cap-
ture condition.
Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (bit CCPxIF is set)
1001 = Compare mode, clear output on match (bit CCPxIF is set)
1010 = Compare mode, generate software interrupt on match (bit CCPxIF is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1)
11xx = PWM mode
U-0
—
CCPxX
R/W-0
CCPxY CCPxM3
R/W-0
R/W-0
CCPxM2
R/W-0
CCPxM1 CCPxM0
R/W-0
FIGURE 10-2: CAPTURE MODE
10.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work consistently.
10.1.3
When the Capture event is changed, a false capture
interrupt may be generated. The user should clear
enable bit CCP1IE (PIE1<2>) to avoid false interrupts
and should clear flag bit CCP1IF following any such
change in operating mode.
RC2/CCP1
pin
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
R/W-0
edge detect
Q’s
Prescaler
1, 4, 16
and
bit0
CCP1CON<3:0>
OPERATION BLOCK
DIAGRAM
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
R = Readable bit
Set CCP1IF
PIR1<2>
1997 Microchip Technology Inc.
read as ‘0’
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L