SDA4336 Infineon Technologies Corporation, SDA4336 Datasheet - Page 16

• Manufacturer Part Number: SDA4336
• Description: PLL Frequency Synthesizer, if Counter, 7 Bit ADC, 7 & 4 Bit DAC With Two Channel Digital Alignment
• Manufacturer: Infineon Technologies Corporation

I
Data Transition:
Start Condition (STA):
Stop Condition (STO):
Acknowlage (ACK):
Data Transfer Write Mode:
Data Transfer Read Mode:
3W bus mode
Semiconductor Group
2
C bus mode
A two channel digital alignment is avialable. Each channel is separatly set by a sloperange from
0.66...2.0 with 7bit resolution additional a offsetvoltage from +/- 0,5V or +/- 1V with 7bit resolution.
The offsetvoltage range is:
U
U
The slope range is:
Slope= 128/(64+n) , n=0...127
The SDA 4336 supports the I
selectable by pin 7: BUS_MODE (I
BUS_ENA) are Schmitt-triggered input buffer for 3V or 5V C.
The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to
high transition of CLK and is shifted out (read mode) on the high to low transition of CLK.
In this mode pin7 (BUS_MODE) = low and pin10 (BUS_ENA)=low. In this mode SDA is a
bidirectional input / output pin.
Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as start or stop condition.
A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high
level.This start condition must precede any command and initiate a data transfer onto the bus.
A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable
high level. This condition terminate the communication between the devices and forces the bus
interface into the initial conditions.
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the
8 bits of data correctly.
To start the communication, the bus master must initiate a start condition, followed by the 8bit chip
address (write). The chip address for the SDA 4336 is fixed as ”1100110” (MSB at first). The last bit
(LSB=A0) of the chip address byte defines the typ of operation to be performed:
A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparision
the SDA 4336 will generate an ACK.
After this device addressing the desired sub address byte and data bytes must be followed. The
subaddresses determines which one of the 11 data bytes (00H...07H,09H .. 0BH) is transmitted first.
At the end of data transition the master must be generate the stop condition.
To start the communication in the read mode, the bus master must initiate a start condition, fol
lowed by the 8bit chip address (write: A0=0), followed by the sub address read (82H or 83H),
followed by the chip address (read: A0=1). After that procedure the 16bit data register 82H or the
8bit data register 83H is read out. After the first 8 bit read out, the uP mandatory send LOW during
the ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock.
At the end of data transition the master must be generate the stop condition.
In this mode pin7 (BUS_MODE) =high. Pin9 (SDA) is a bidirectional input / output pin in this mode.
Pin10 (BUS_ENA) is used to activate the bus interface to allow the transfer of data to / from the
device. When BUS_ENA is in an inactive high state, shifting is inhibited.
OFFSET
OFFSET
= +/-1V*(n/127), n=0...127, for bit D15=high in subaddresses 09H or 0AH
= +/-0,5V*(n/127), n=0...127, for bit D15=low in subaddresses 09H or 0AH
2
C bus protocol (2 wire) or 3 Wire bus protocol operation
2
C=low, 3W=high). All bus pins ( BUS_MODE, SCL, SDA,
Specification
direction is set by bit 7in subaddress 09H or 0AH
16
SDA 4336
21.5.99