PIC18LF13K22 Microchip Technology, PIC18LF13K22 Datasheet
PIC18LF13K22
Available stocks
Related parts for PIC18LF13K22
PIC18LF13K22 Summary of contents
Page 1
... Flash Memory Programming Specification 1.0 DEVICE OVERVIEW This document includes specifications for the following devices: • PIC18F13K22 • PIC18LF13K22 • PIC18F14K22 • PIC18LF14K22 2.0 PROGRAMMING OVERVIEW The PIC18F1XK22/LF1XK22 devices can be pro- grammed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the low-voltage ICSP method. Both methods can be done with the device in the users’ ...
Page 2
... All power supply (V DS41357A-page 2 During Programming Pin Type P Programming Enable P Power Supply P Ground I Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’ I Serial Clock I/O Serial Data ) and ground (V ) pins must be connected Advance Information Pin Description © 2008 Microchip Technology Inc. (1) ...
Page 3
... FIGURE 2-1: 20-PIN PDIP, SSOP AND SOIC PIN DIAGRAM FOR PIC18F1XK22/LF1XK22 20-pin PDIP, SSOP, SOIC (300 MIL) RA5/OSC1/CLKIN/T13CKI RA4/AN3/OSC2/CLKOUT RC3/AN7/C12IN3-/P1C/PGM 20-Pin QFN 4x4 © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 RA3/MCLR RC5/CCP1/P1A 5 RC4/C2OUT/P1B/SRQ 6 7 RC6/AN8/SS 8 RC7/AN9/SDO 9 RB7/TX/ ...
Page 4
... IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F13K22/ 000000h-001FFFh (8K) LF13K22 PIC18F14K22/ 000000h-003FFFh (16K) LF14K22 Address Range BBSIZ = 0 000000h (2) Boot Block 0007FFh 000800h 000FFFh 001000h Block 0 001FFFh 002000h Block 1 003FFFh 004000h Unimplemented Read ‘0’s 01FFFFh © 2008 Microchip Technology Inc. ...
Page 5
... MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18F13K22/LF13K22 DEVICES 000000h 01FFFFh 200000h 3FFFFFh Note 1: Sizes of memory areas are not to scale. 2: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 (1) Code Memory MEMORY SIZE/DEVICE 8 Kbytes (PIC18F13K22) BBSIZ = 1 Unimplemented Read as ‘ ...
Page 6
... ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h 300004h CONFIG3H 300005h CONFIG4L 300006h 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh © 2008 Microchip Technology Inc. ...
Page 7
... Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.2 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 3-6, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V (high voltage) ...
Page 8
... PGM PGD PGC PGD = Input DS41357A-page 8 FIGURE 3-9: P17 bit is ‘1’ (see /RA3 P12 Advance Information EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P18 V MCLR/V /RA3 PGM V IH PGD PGC PGD = Input © 2008 Microchip Technology Inc. ...
Page 9
... Table Read Table Read, post-increment Table Read, post-decrement Table Read, pre-increment Table Write Table Write, post-increment by 2 Table Write, start programming, post-increment by 2 Table Write, start programming © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4-Bit Command 0000 0010 1000 1001 1010 1011 ...
Page 10
... Core Instruction P2A P2B 16-bit Data Payload PGD = Input Advance Information P5A Fetch Next 4-bit Command © 2008 Microchip Technology Inc. n ...
Page 11
... PGC after the NOP command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle but PGD must be held low. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The code sequence to erase the entire device is shown in Table 4-2 and the flowchart is shown in Figure 4-1. ...
Page 12
... EEPROM write timing shown in Figure 4-7. Note: Advance Information P10 P5A P11 16-bit Erase Time 4-bit Command Data Payload ICSP ROW ERASE The TBLPTR register can point at any byte within the row intended for erase. © 2008 Microchip Technology Inc ...
Page 13
... Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased. Step 7: Disable writes 0000 Note 1: See Figure 5-4 for details on shift out data timing. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS ...
Page 14
... PIC18F1XK22/LF1XK22 www.DataSheet4U.com FIGURE 4-3: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 DS41357A-page 14 Start Addr = 0 Configure Device for Row Erases Perform Erase Sequence No WR Bit Clear? Yes All No Rows done? Yes Done Advance Information © 2008 Microchip Technology Inc. ...
Page 15
... To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array ...
Page 16
... Command PGD = Input Advance Information Start LoopCount = 0 Configure Device for Writes to Write All bytes written? Yes All locations done? Yes Done P10 ( Programming Time Data Payload © 2008 Microchip Technology Inc 16-bit ...
Page 17
... Table 4-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 8: Disable writes. 0000 © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 5.2 “ ...
Page 18
... Start Write Sequence No WR bit clear? Yes No done? Yes Done P10 P11A Poll WR bit, Repeat until Clear 16-bit Data Payload (see below P5A 0 Shift Out Data MOVWF TABLAT (see Figure 4-4) PGD = Output © 2008 Microchip Technology Inc ...
Page 19
... Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 Repeat steps 2 through 8 to write more data. Note 1: See Figure 5-4 for details on shift out data timing. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 9E A6 BCF EECON1, EEPGD 9C A6 BCF EECON1, CFGS MOVLW < ...
Page 20
... Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Advance Information © 2008 Microchip Technology Inc. ...
Page 21
... Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 4-8: CONFIGURATION PROGRAMMING FLOW Delay P9 and P10 © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4.6 Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘ ...
Page 22
... P6 P14 LSb PGD = Input Advance Information Core Instruction P5A (Note MSb Fetch Next 4-bit Command Shift Data Out PGD = Output PGD = Input © 2008 Microchip Technology Inc ...
Page 23
... Word = Expect data? All No code memory verified? © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command can not be used to increment the Table Pointer beyond the code memory space ...
Page 24
... BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR BSF EECON1, RD MOVF EEDATA MOVWF TABLAT NOP (1) Shift Out Data Advance Information READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No done? Yes Done © 2008 Microchip Technology Inc. ...
Page 25
... PGD via the 4-bit command, ‘0010’ (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 5.4 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 ...
Page 26
... LVP — STVREN 10-- 01-1 — CP1 CP0 ---- --11 — — — 11-- ---- — WRT1 WRT0 ---- --11 — — — 111- ---- — EBTR1 EBTR0 ---- --11 — — — -1-- ---- REV2 REV1 REV0 See Table 6-2 DEV5 DEV4 DEV3 See Table 6-2 © 2008 Microchip Technology Inc. ...
Page 27
... TABLE 6-2: DEVICE ID VALUE Device PIC18LF13K22 PIC18LF14K22 PIC18F13K22 PIC18F14K22 Note: The ‘x’s in DEVID1 contain the device revision code. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Device ID Value DEVID2 4Fh 4Fh 4Fh 4Fh Advance Information DEVID1 100x xxxx 011x xxxx 010x xxxx ...
Page 28
... Brown-out Reset enabled in hardware only and disabled in Sleep mode SBOREN is disabled Brown-out Reset enabled and controlled by software (SBOREN is enabled Brown-out Reset disabled in hardware and software Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Advance Information Description © 2008 Microchip Technology Inc. ...
Page 29
... Bit Name WDPS<3:0> WDTEN MCLRE HFOFST ENHCPU BBSIZ LVP STVREN CP1 CP0 CPD . © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Configuration Words CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 ...
Page 30
... These bits are used with the DEV<2:0> bits in the DEVID1 register to identify part number. Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. Revision ID bits These bits are used to indicate the revision of the device. Advance Information Description © 2008 Microchip Technology Inc. ...
Page 31
... EEPROM information must be included. An option to not include the data EEPROM information may be pro- vided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 7.2 Checksum Computation The checksum is calculated by summing the following: • ...
Page 32
... Code-Protect Device BBSIZ = 0 None Boot Block PIC18F14K22/ PIC18LF14K22 Boot/ Block 0 All None Boot Block PIC18F13K22/ PIC18LF13K22 Boot/ Block 0 All Legend: Item Description CONFIGx = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & ...
Page 33
... CY PWRT + 1.5 μs (for EC mode only) where the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data OSC sheet for the particular device. © 2008 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Characteristic /RA3 /RA3 /RA3 PP /RA3 Rise Time to enter ...
Page 34
... PIC18F1XK22 Only. Refer to Figure 2.1.1. — ns μs — PIC18F1XK22 Only. Refer to Figure 2.1.1. — ns μs — — s 100 ns — μs — and V ; this can cause spurious program IHH is the Power-up Timer period and PWRT © 2008 Microchip Technology Inc. ...
Page 35
... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U ...
Page 36
... Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/02/08 © 2008 Microchip Technology Inc. ...