AD1849K Analog Devices, AD1849K Datasheet - Page 18

• Manufacturer Part Number: AD1849K
• Description: Serial-Port 16-Bit SoundPort Stereo Codec
• Manufacturer: Analog Devices

AD1849K
TSIN is sampled on the falling edge of SCLK. A LO-to-HI
transition of TSIN defines the beginning of the word to occur at
the next rising edge of SCLK (for driving output data). The
LO-to-HI transition is defined by consecutive LO and HI
samples of TSIN at the falling edges of SCLK. Both input and
output data will be valid at the immediately subsequent falling
edge of SCLK. See Figures 6 and 7.
After the beginning of a word has been recognized, TSIN is a
“don’t care”; its state will be ignored until one SCLK period
before the end of the current word.
16-BIT STEREO DATA WORD
63
16-BIT MONO DATA WORD
63
8-BIT STEREO DATA WORD
63
8-BIT MONO DATA WORD
63
CONTROL WORD
63 61 60
FSYNC, TSIN, &
Left Audio 0000 0000 Right Audio 0000 0000
Left Audio
001 MB OLB DCB 0 AC
SDRX & SDTX
Left-Channel Audio
Left-Channel Audio
TSOUT
Figure 6. AD1849K Timing Relationships
SCLK
56
56
59
55
55
0000 0000 Left Audio 0000 0000
58 57 56 55 54 53 51 50 49 48 47 46 44 43 42 41
48 47
48 47
48 47
Right-Channel Audio
Left-Channel Audio
00
40
DFR ST DF ITS MCK FSEL MS TXDIS 0000 00 ENL ADL PIO 00 0000 0000 0000 0010 REVID 0000 0000
39
Figure 8. AD1849K Bit Positions for Data and Control
FIRST DATA BIT
32 31
32 31 30 29 24 23 22 21
32 31 30 29 24 23 22 21
OF WORD
32 31 30 29 24 23 22 21
OM
OM
OM
OM
30 29 24 23 22 21
LO
LO
LO
LO
ADI SM
ADI SM
ADI SM
ADI SM
–18–
RO
RO
RO
RO
40
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
The AD1849K comes out of reset with the default conditions
specified in “Control Register Defaults.” It will be in the mode
specified by the D/C pin. If in Control Mode, the SoundPort
Codec can be configured by the host for operation. Subsequent
transitions to Control Mode after initialization are expected to
be relatively infrequent. Control information that is likely to
change frequently, e.g., gain levels, is transmitted along with the
data in Data Mode. See Figure 8 for a complete map of the data
and control information into the 64-bit Data Word and the
64-bit Control Word.
SDRX AND TSIN
INPUTS
SDTX CONTROL
OR DATA BYTE 1,
BIT 7 OUTPUT
SDTX CONTROL
OR DATA BYTE 8,
BIT 0 OUTPUT
PIO
INPUTS
PIO
OUTPUTS
SCLK
SDTX, FSYNC,
AND TSOUT
OUTPUTS
PIO
PIO
39
PIO
PIO
34 33
OVR
OVR
OVR
OVR
Figure 7. AD1849K Timing Parameters
IS
IS
12 11 8 7 4 3 0
12 11 8 7 4 3 0
IS
12 11 8 7 4 3 0
IS
12 11 8 7 4 3 0
32 31 30
LG
LG
LG
LG
MA
MA
MA
MA
29 24 23
t
t
ZV
D
t
HI
0000
0000
t
RG
S
RG
t
CLK
t
t
IH
D
t
16 15 12 11
t
t
LO
OH
VZ
t
S
t
IH
t
OH
8 7
REV. 0
0