XC2S100E-6FG456I Xilinx, XC2S100E-6FG456I Datasheet

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XC2S100E-6FG456I

Manufacturer Part Number
XC2S100E-6FG456I
Description
Spartan-IIE 1.8V FPGA Family
Manufacturer
Xilinx
Datasheet

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XC2S100E-6FG456I
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DS077-1 (v1.0) November 15, 2001
Introduction
The Spartan™-IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an exceptionally low
price. The five-member family offers densities ranging from
50,000 to 300,000 system gates, as shown in
tem performance is supported beyond 200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
Table 1: Spartan-IIE FPGA Family Members
DS077-1 (v1.0) November 15, 2001
Preliminary Product Specification
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S50E
Device
Second generation ASIC replacement technology
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© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities as high as 6,912 logic cells with up to
300,000 system gates
Streamlined features based on Virtex-E
architecture
Unlimited in-system reprogrammability
Very low cost
development
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Logic
Cells
1,728
2,700
3,888
5,292
6,912
cycles,
System Gate Range
(Logic and RAM)
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
23,000 - 50,000
R
Typical
and
inherent
Table
(R x C)
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
Array
risk
CLB
1. Sys-
0
0
www.xilinx.com
1-800-255-7778
of
0
CLBs
1,176
1,536
Total
384
600
864
Spartan-IIE 1.8V FPGA Family:
Introduction and Ordering
Information
Preliminary Product Specification
System level features
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Versatile I/O and packaging
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Fully supported by powerful Xilinx ISE development
system
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Maximum
Available
User I/O
SelectRAM+™ hierarchical memory:
·
·
·
Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Low cost packages available in all densities
Family footprint compatibility in common packages
19 high-performance interface standards, including
LVDS and LVPECL
Up to 120 differential I/O pairs that can be input,
output, or bidirectional
Zero hold time simplifies system timing
Fully automatic mapping, placement, and routing
Integrated with design entry and verification tools
182
202
263
289
329
16 bits/LUT distributed RAM
Configurable 4K-bit true dual-port block RAM
Fast interfaces to external RAM
Differential
Maximum
I/O Pairs
114
120
120
84
86
Distributed
RAM Bits
24,576
38,400
55,296
75,264
98,304
RAM Bits
Block
32K
40K
48K
56K
64K
1

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XC2S100E-6FG456I Summary of contents

Page 1

... Very low cost Table 1: Spartan-IIE FPGA Family Members Typical Logic System Gate Range Device Cells (Logic and RAM) XC2S50E 1,728 23,000 - 50,000 XC2S100E 2,700 37,000 - 100,000 XC2S150E 3,888 52,000 - 150,000 XC2S200E 5,292 71,000 - 200,000 XC2S300E 6,912 93,000 - 300,000 © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. The Xilinx XC17S00A PROM family is recommended for serial configuration of Spartan-IIE FPGAs. The XC18V00 reprogrammable PROM family is recommended for parallel or serial configuration ...

Page 3

... J 2. Parentheses indicate product not yet released. Contact sales for availability. Table 3: Spartan-IIE User I/O Chart Maximum Device User I/O TQ144 XC2S50E 182 XC2S100E 202 XC2S150E 263 XC2S200E 289 XC2S300E 329 DS077-1 (v1.0) November 15, 2001 Preliminary Product Specification Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information ...

Page 4

... Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information Ordering Information Example: Device Type Speed Grade Device Ordering Options Device Speed Grade XC2S50E -6 Standard Performance XC2S100E -7 Higher Performance XC2S150E XC2S200E XC2S300E Revision History Version No. Date 1.0 11/15/01 Initial Xilinx release. The Spartan-IIE Family Data Sheet DS077-1, Spartan-IIE 1 ...

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