MT5C1005 ASI, MT5C1005 Datasheet

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MT5C1005

Manufacturer Part Number
MT5C1005
Description
SRAM MEMORY ARRAY
Manufacturer
ASI
Datasheet

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MT5C1005
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MT5C1005C-20/883
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MT5C1005C-25
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256K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
•MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS double-metal
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
• Package(s)
• Operating Temperature Ranges
• 2V data retention/low power
45ns access devices.
SPECIFICATIONS
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
Ceramic DIP (400 mil)
Ceramic Quad LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Industrial (-40
Military (-55
*Electrical characteristics identical to those provided for the
process
For more products and information
www.austinsemiconductor.com
please visit our web site at
o
C to +125
o
C to +85
o
(contact factory)
o
C)
C)
MARKING
F
L
-20
-25
-35
-45
-55*
-70*
C
ECW
EC
DCJ
IT
XT
No. 303
No. 109
No. 206
No. 207
No. 501
A 1 2
A 1 0
A 1 1
A 1 3
A 1 4
A 1 5
A 1 6
A 1 7
CE\
OE\
Vss
NC
NC
A 7
A 8
A 9
GENERAL DESCRIPTION
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology.
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
and all inputs and outputs are fully TTL compatible.
32-Pin Flat Pack (F)
28-Pin DIP (C)
A10
A11
A12
A13
A14
A15
A16
A17
OE\
CE\
Vss
A7
A8
A9
(400 MIL)
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
The Austin Semiconductor SRAM family employs
For flexibility in high-speed memory applications, ASI
All devices operation from a single +5V power supply
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN ASSIGNMENT
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
(Top View)
Vcc
A 6
A 5
A 2
A 4
A 3
A 1
NC
NC
A 0
NC
DQ4
DQ3
DQ2
DQ1
WE\
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
A 1 5
A 1 6
A 1 7
CE\
A12
A10
A11
A13
A14
A15
A16
A17
OE\
CE\
Vss
NC
NC
A7
A8
A9
32-Pin LCC (ECW)
32-Pin SOJ (DCJ)
1 0
1 1
1 2
1 3
32-Pin LCC (EC)
5
6
7
8
9
MT5C1005
14 15 16 17 18 19 20
4 3 2 1 31 32 30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A 2
A 4
A 3
A 1
A 0
NC
NC
NC
DQ4

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MT5C1005 Summary of contents

Page 1

... CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible. MT5C1005 PIN ASSIGNMENT (Top View) 32-Pin LCC (EC) 32-Pin SOJ (DCJ) ...

Page 2

... MEMORY ARRAY COLUMN DECODER TRUTH TABLE MODE STANDBY READ READ WRITE GND OE\ CE\ WE HIGH-Z STANDBY HIGH MT5C1005 DQ4 DQ1 CE\ OE\ WE\ POWER DOWN POWER ACTIVE ACTIVE ACTIVE ...

Page 3

... All Other Inputs IH I SBT2 , V = MAX IH CC -0.2V MAX CC CC < V +0. SBC -0.2V Hz* CC CONDITIONS 25° 1MHz MT5C1005 MAX UNITS NOTES +0 0 µA 10 µ 0 MAX -20 -25 -35 -45 UNITS NOTES 180 180 180 180 ...

Page 4

... LZOE t 8 HZOE LZWE HZWE MT5C1005 -25 -35 - ...

Page 5

... CC and CCDR -0.2V CDR t R DATA RETENTION MODE 4.5V V > CDR V DR MT5C1005 167 167 1.73V TH 30pF 5pF Fig. 2 Output Load Equivalent Equivalent t t LZCE, and HZWE is less than t t HZOE is less than LZOE. MIN MAX UNITS NOTES ...

Page 6

... AA t tOH READ CYCLE NO tRC tRC RC t tAOE AOE t tACE ACE DATA VALID MT5C1005 8, 9 DATA VALID t tHZOE HZOE t tHZCE HZCE t tPD DON’T CARE UNDEFINED ...

Page 7

... CW t tWP1 tWP1 WP DATA VALID HIGH-Z MT5C1005 tAH ...

Page 8

... Pin 1 SYMBOL *All measurements are in inches ASI PACKAGE SPECIFICATIONS MIN MAX 0.090 0.110 0.016 0.020 0.040 0.060 0.008 0.012 1.386 1.414 0.385 0.405 0.390 0.410 0.090 0.110 0.125 0.175 0.040 0.060 MT5C1005 ...

Page 9

... *All measurements are in inches ASI PACKAGE SPECIFICATIONS MIN 0.077 0.022 0.004 0.054 0.742 0.395 0.442 0.295 0.045 0.045 0.077 MT5C1005 MAX 0.093 0.028 0.014 0.066 0.758 0.405 0.458 0.305 0.055 0.055 0.093 ...

Page 10

... ASI Case #207 (Package Designator EC SYMBOL *All measurements are in inches ASI PACKAGE SPECIFICATIONS MIN 0.080 0.022 0.004 0.054 0.815 0.392 0.045 0.070 0.090 MT5C1005 A b2 MAX 0.100 0.028 0.014 0.066 0.835 0.408 0.055 0.080 0.110 ...

Page 11

... *All measurements are in inches ASI PACKAGE SPECIFICATIONS MIN --- 0.015 0.004 0.812 0.745 0.405 0.324 0.045 0.290 0.027 MT5C1005 Pin 1 Index Bottom View A Q MAX 0.125 0.019 0.006 0.828 0.755 0.415 0.336 0.055 0.310 0.033 ...

Page 12

... ASI Case #501 (Package Designator DCJ SYMBOL *All measurements are in inches ASI PACKAGE SPECIFICATIONS MIN 0.135 0.026 0.015 0.812 0.740 0.405 0.045 0.435 0.360 0.030 MT5C1005 MAX 0.153 0.036 0.019 0.828 0.755 0.415 0.055 0.445 0.380 0.040 ...

Page 13

... EXAMPLE: MT5C1005C-20L/IT Device Package Speed Options** Process Number Type ns MT5C1005 C -20 MT5C1005 C -25 MT5C1005 C -35 MT5C1005 C -40 MT5C1005 C -55 MT5C1005 C -70 EXAMPLE: MT5C1005F-25L/883C Device Package Speed Options** Process Number Type ns MT5C1005 F -20 MT5C1005 F -25 MT5C1005 F -35 MT5C1005 F -40 MT5C1005 F -55 MT5C1005 ...

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