P123-042 PhaseLink Corp., P123-042 Datasheet

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P123-042

Manufacturer Part Number
P123-042
Description
3.3v Zero Delay Buffer
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 1
AVAILABLE CONFIGURATIONS
PL123-042
PL123-042
PL123-04
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
Multiple configurations, see “Available Configura-
tions” table
Multiple low-skew outputs
10 MHz to 134 MHz operating range
Low cycle-to-cycle jitter
8 pin SOP package
3.3V operation
Commercial and industrial temperature available
REF
Device
Bank A or Bank B
Feedback From
Bank A
Bank B
Divider
(-042)
Extra
PLL
Bank A Frequency
2 x Reference
/2
Reference
Reference
Bank B Frequency
FBK
CLKA1
CLKA2
CLKB1
CLKB2
DESCRIPTION
The PL123-04 is a PLL-based zero-delay buffer, used
to distribute up to four outputs. An external feedback
pin enables removing delay from external components.
It also provides adjustable input-to-output delay by
varying its loading relative to the output pin loading.
The PL123-042 option allows the user to obtain x1, x2,
or x0.5 frequencies on the output bank. The exact mul-
tiplier depends on which output is connected to the
FBK pin. Refer to the Available Configurations table
below for more details.
These parts are not intended for 5V input-tolerant ap-
plications.
Reference / 2
Reference
Reference
(Preliminary)
CLKA1
CLKA2
3.3V Zero Delay Buffer
VDD
REF
1
2
3
4
8 Pin SOP
Top View
PL123-04
8
7
6
5
FBK
VDD
CLKB2
CLKB1

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P123-042 Summary of contents

Page 1

FEATURES • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available Configura- tions” table • Multiple low-skew outputs • 10 MHz to 134 MHz operating range • Low cycle-to-cycle jitter • 8 pin ...

Page 2

PIN DESCRIPTION Pin Name Type 1 REF I [1] 2 CLKA1 O [2] 3 CLKA2 O [2] 4 GND P 5 CLKB1 O [2] 6 CLKB2 O [2] 7 VDD P 8 FBK I Notes: 1: Weak pull-down. 2: Weak ...

Page 3

LAYOUT RECOMMENDATIONS The following guidelines assist in optimizing a PCB design: Signal Integrity and Termination Considerations - Keep traces short - Trace = Inductor. Adding a capacitive load may cause ringing. - Long trace = Transmission Line. Without proper termination ...

Page 4

OPERATING CONDITIONS Parameter Description V Supply Voltage DD Commercial Operating Temperature (ambient temperature Industrial Operating Temperature (ambient temperature) Load Capacitance, below 100 MHz C L Load Capacitance, above 100 MHz C Input Capacitance IN Power-up time for all ...

Page 5

SWITCHING CHARACTERISTICS Pa- Name rameter t Output Frequency 1 t Output Frequency 1 Duty Cycle = t2 ÷ t1 [4] Duty Cycle = t2 ÷ t1 [4] t Rise Time [ Fall Time [4] 4 Output to Output ...

Page 6

SWITCHING WAVEFORMS Duty Cycle Timing All Outputs Rise/Fall Time Output-Output Skew Input-Output Propagation Delay Device-Device Skew 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 1.4V 2.0V OUTPUT 0.8V t ...

Page 7

TEST CIRCUIT 0.1 μF 0.1 μF PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) 8-Pin SOP Dimension in MM Symbol Min. A 1.35 A1 0.10 A2 1.25 B 0.33 C 0.19 D 4.80 E 3.80 H 5.80 L 0.40 e 1.27 BSC 47745 ...

Page 8

... SOP (Tape and Reel) Not Green Packages P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and Reel) P123-042 8-Pin SOP Tube P123-042 8-Pin SOP (Tape and Reel) P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and Reel) P123-042 8-Pin SOP Tube ...

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