P130-69 PhaseLink Corp., P130-69 Datasheet

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P130-69

Manufacturer Part Number
P130-69
Description
High Speed Translator Buffers Single Ended To Pecl Or Lvds
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
• Differential PECL (PLL130-68) or LVDS
• Accepts any single-ended REFIN input (with
• Internal AC coupling of REFIN
• Input range from 1.0MHz to 1.0 GHz.
• No Vref required.
• No external current source required.
• 2.5 to 3.3V operation.
• Available in 3x3mm QFN.
DESCRIPTION
The PLL130-68 and PLL130-69 are low cost,
high performance, high speed, translator buffers
that reproduce any input frequency from DC to
1.0GHz. They provide a pair of differential out-
puts (PECL for PLL130-68 or LVDS for PLL130-
69). Thanks to an internal AC coupling of the
reference input (REFIN), any input signal with at
least 100mV swing can be used as reference
signal, regardless of its DC value. These chips
are ideal for conversion from clipped sine wave,
TTL, CMOS, or differential signal to LVDS or
PECL.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
(PLL130-69) output.
as low as 100mV swing).
REFIN
Coupling
AC
High Speed Translator Buffers: Single ended to PECL or LVDS
Amplifier
Input
OUTPUT ENABLE LOGICAL LEVELS
PLL130-68
OECTRL input: Logical states defined by PECL levels.
PLL130-69
OECTRL input: Logical states defined by CMOS levels.
0 (Default)
0 (Default)
OESEL
OESEL
1
1
REFIN
PIN CONFIGURATION
NC
NC
NC
0 (Default)
1 (Default)
1 (Default)
0 (Default)
OECTRL
OECTRL
PLL130-68/-69
(TOP VIEW)
1
0
0
1
2
3
1
4
16
PLL130-6x
5
Q
Q_BAR
15
6
14
7
13
8
OUTPUT STATE
OUTPUT STATE
Output enabled
Output enabled
Output enabled
Output enabled
12
11
10
9
Tri-state
Tri-state
Tri-state
Tri-state
NC
Q
Q_bar
OESEL

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P130-69 Summary of contents

Page 1

High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES • Differential PECL (PLL130-68) or LVDS (PLL130-69) output. • Accepts any single-ended REFIN input (with as low as 100mV swing). • Internal AC coupling of REFIN • Input range ...

Page 2

High Speed Translator Buffers: Single ended to PECL or LVDS PIN DESCRIPTION Name Pin number 12, 14 REFIN 2 OECTRL 5 GND 7 OESEL 9 Q_BAR VDD Q_BAR ...

Page 3

High Speed Translator Buffers: Single ended to PECL or LVDS 3. AC Specifications PARAMETERS Input Frequency Input signal swing Output Frequency 4. PECL Electrical Characteristics PARAMETERS SYMBOL Output High Voltage Output Low Voltage 5. PECL Switching Characteristics PARAMETERS Clock Rise ...

Page 4

High Speed Translator Buffers: Single ended to PECL or LVDS 6. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V Magnitude Change DD Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current 7. ...

Page 5

... Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 5 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL130- Marking P130-68 P130-68 P130-69 P130-69 PLL130-68/-69 TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE Q=QFN Package Option QFN - Tape and Reel ...

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