MC14015B ON Semiconductor, MC14015B Datasheet

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MC14015B

Manufacturer Part Number
MC14015B
Description
Dual 4-Bit Static Shift Register
Manufacturer
ON Semiconductor
Datasheet

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MC14015B
Dual 4-Bit Static
Shift Register
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14015B dual 4–bit static shift register is constructed with
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
Schottky TTL Load Over the Rated Temperature Range.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design —
Capable of Driving Two Low–power TTL Loads or One Low–power
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14015BCP
MC14015BD
MC14015BDR2
MC14015BDT
MC14015BF
MC14015BFEL
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
CASE 751B
SOEIAJ–16
CASE 948F
DT SUFFIX
CASE 648
TSSOP–16
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
SOIC–16
SOEIAJ–16
SOEIAJ–16
PDIP–16
TSSOP–16 2000/Tape & Reel
= Assembly Location
Package
SOIC–16
SOIC–16
PDIP–16
Publication Order Number:
2500/Tape & Reel
16
16
16
1
1
1
MC14015BCP
DIAGRAMS
See Note 1.
MARKING
See Note 1.
AWLYYWW
MC14015B
AWLYWW
16
AWLYWW
Shipping
2000/Box
1
MC14015B/D
14015B
48/Rail
ALYW
015B
14

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MC14015B Summary of contents

Page 1

... MC14015B Dual 4-Bit Static Shift Register The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. ...

Page 2

... MC14015B TRUTH TABLE Change Don’t Care Q = Q0, Q1, Q2, or Q3, as applicable Output of prior stage. n–1 PIN ASSIGNMENT ...

Page 3

... I (50 pF – 50) Vfk where (per package pF MC14015B (Voltages Referenced Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î – Î Î Î ...

Page 4

... Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. CLOCK DATA Figure 1. Power Dissipation Test Circuit and Waveform MC14015B = pF Î ...

Page 5

... Figure 2. Switching Test Circuit and Waveforms V DD PULSE GENERATOR SYNC Q2 PULSE C Q3 GENERATOR Figure 3. Setup and Hold Time Test Circuit and Waveforms MC14015B DATA INPUT t TLH CLOCK C L INPUT 50% Duty Cycle WL WH ...

Page 6

... MC14015B CIRCUIT SCHEMATICS http://onsemi.com 6 ...

Page 7

... C Q CLOCK INPUT BUFFER RESET INPUT BUFFER Q0 DATA INPUT BUFFER CLOCK INPUT BUFFER RESET INPUT BUFFER MC14015B LOGIC DIAGRAMS SINGLE BIT COMPLETE DEVICE ...

Page 8

... SEATING –T– PLANE 0.25 (0.010 MC14015B PDIP–16 P SUFFIX NOTES: CASE 648–08 1. DIMENSIONING AND TOLERANCING PER ANSI ISSUE R Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 9

... G K –T– SEATING PLANE 0.25 (0.010 MC14015B PACKAGE DIMENSIONS SOIC–16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE 0.25 (0.010 http://onsemi.com 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 10

... L PIN 1 IDENT. 1 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING D G PLANE MC14015B PACKAGE DIMENSIONS TSSOP–16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F–01 ISSUE Ç Ç Ç É É É J1 Ç Ç Ç ...

Page 11

... PLASTIC EIAJ SOIC PACKAGE VIEW 0.10 (0.004) 0.13 (0.005) M MC14015B PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX CASE 966–01 NOTES: ISSUE DETAIL P c http://onsemi.com 11 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

Page 12

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 MC14015B/D ...

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