MC14515 ON Semiconductor, MC14515 Datasheet

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MC14515

Manufacturer Part Number
MC14515
Description
4-Bit Transparent Latch/4-to-16 Line Decoder
Manufacturer
ON Semiconductor
Datasheet

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MC14514B, MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R–S type flip–flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4–bit latch/4 to 16 line decoder are
constructed with N–channel and P–channel enhancement mode
devices in a single monolithic structure. The latches are R–S type
flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
applications where low power dissipation and/or high noise immunity
is desired.
1. Maximum Ratings are those values beyond which damage to the device
2. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14514B and MC14515B are two output options of a 4 to 16
These complementary circuits find primary use in decoding
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 2.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 1.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
MC14514BCP
MC14514BDW
MC14514BDWR2
MC14515BCP
MC14515BDW
MC14515BDWR2
Device
DW SUFFIX
CASE 751E
CASE 709
P SUFFIX
SOIC–24
PDIP–24
ORDERING INFORMATION
XX
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
= Specific Device Code
= Assembly Location
Package
SOIC–24
SOIC–24
SOIC–24
SOIC–24
PDIP–24
PDIP–24
24
24
1
1
Publication Order Number:
MC145XXBCP
AWLYYWW
AWLYYWW
145XXB
1000/Tape & Reel
1000/Tape & Reel
DIAGRAMS
MARKING
Shipping
MC14514B/D
15/Rail
30/Rail
15/Rail
30/Rail

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MC14515 Summary of contents

Page 1

... MC14514B, MC14515B 4-Bit Transparent Latch/4-to-16 Line Decoder The MC14514B and MC14515B are two output options line decoder with latched inputs. The MC14514B (output active high option) presents a logical “1” at the selected output, whereas the MC14515B (output active low option) presents a logical “0” at the selected output. The latches are R– ...

Page 2

... All Outputs = 0, MC14514 All Outputs = 1, MC14515 X = Don’t Care *Strobe = 0, Data is latched BLOCK DIAGRAM V = PIN PIN DATA DATA 2 TRANSPARENT LATCH DECODER DATA ...

Page 3

... The formulas given are for the typical characteristics only calculate total supply current at loads other than 50 pF (50 pF – 50) Vfk where (per package pF MC14514B, MC14515B (Voltages Referenced – Vdc Min Max Min V 5.0 — ...

Page 4

... V DS For MC14515B 1. For P–channel: Inhibit = For N–channel: Inhibit = and D1–D4 constitute binary 2. code for “output under test.” EXTERNAL ...

Page 5

... I D PULSE D1 GENERATOR STROBE INHIBIT Figure 2. Dynamic Power Dissipation Test Circuit and Waveform STROBE INHIBIT D1 PROGRAMMABLE PULSE GENERATOR Figure 3. Switching Time Test Circuit and Waveforms MC14514B, MC14515B V DD 0.01 F CERAMIC 500 10% S15 ...

Page 6

... MC14514B, MC14515B http://onsemi.com 6 ...

Page 7

... REGISTER 8 DATA SELECT REGISTER 9 REGISTER 16 MC14514B, MC14515B COMPLEX DATA ROUTING times faster then the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers ...

Page 8

... MC14514B, MC14515B PACKAGE DIMENSIONS SEATING PLANE G D PDIP–24 P SUFFIX PLASTIC DIP PACKAGE CASE 709–02 ISSUE C NOTES POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL ...

Page 9

... D 24X 0.010 (0.25 –T– SEATING PLANE G 22X MC14514B, MC14515B PACKAGE DIMENSIONS SOIC–24 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E P 12X 0.010 (0.25 http://onsemi.com ...

Page 10

... Notes MC14514B, MC14515B http://onsemi.com 10 ...

Page 11

... Notes MC14514B, MC14515B http://onsemi.com 11 ...

Page 12

... English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland MC14514B, MC14515B CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – ...

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