MC14520B

Manufacturer Part NumberMC14520B
Description(MC14518B / MC14520B) Dual Up Counters
ManufacturerON Semiconductor
MC14520B datasheet
 


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MC14518B, MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P−channel and N−channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4−stage
counters. The counter stages are type D flip−flops, with interchangeable
Clock and Enable lines for incrementing on either the positive−going or
negative−going transition as required when cascading multiple stages.
Each counter can be cleared by applying a high level on the Reset line.
In addition, the MC14518B will count out of all undefined states within
two clock periods. These complementary MOS up counters find
primary use in multi−stage synchronous or ripple counting applications
requiring low power dissipation and/or high noise immunity.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Internal and External Speeds
Logic Edge−Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition on Enable
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
, V
Input or Output Voltage Range
in
out
(DC or Transient)
I
, I
Input or Output Current
in
out
(DC or Transient) per Pin
P
Power Dissipation,
D
per Package (Note 2.)
T
Operating Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature
L
(8−Second Soldering)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
v (V
) v V
to the range V
or V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
or V
). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 5
www.DataSheet4U.com
) (Note 1.)
SS
Value
Unit
−0.5 to +18.0
V
−0.5 to V
+ 0.5
V
DD
±10
mA
500
mW
°C
−55 to +125
See detailed ordering and shipping information in the package
°C
−65 to +150
dimensions section on page 7 of this data sheet.
°C
260
and V
should be constrained
in
out
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
MC145xxBCP
P SUFFIX
AWLYYWWG
CASE 648
1
16
SOIC−16
145xxB
DW SUFFIX
AWLYYWWG
CASE 751G
1
16
SOEIAJ−16
MC145xxB
F SUFFIX
ALYWG
CASE 966
1
xx
= 18 or 20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Indicator
ORDERING INFORMATION
Publication Order Number:
MC14518B/D

MC14520B Summary of contents

  • Page 1

    ... MC14518B, MC14520B Dual Up Counters The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4−stage counters. The counter stages are type D flip−flops, with interchangeable Clock and Enable lines for incrementing on either the positive− ...

  • Page 2

    ... MC14518B, MC14520B PIN ASSIGNMENT BLOCK DIAGRAM CLOCK ENABLE R 7 CLOCK ENABLE PIN PIN 8 ...

  • Page 3

    ... The formulas given are for the typical characteristics only at 25_C calculate total supply current at loads other than 50 pF (50 pF μA (per package), C where pF MC14518B, MC14520B (Voltages Referenced − 55_C V DD Vdc Min Max Min Symbol V 5.0 — ...

  • Page 4

    ... Reset Removal Time 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Figure 1. Power Dissipation Test Circuit and Waveform MC14518B, MC14520B (6 pF, T ...

  • Page 5

    ... GENERATOR Figure 2. Switching Time Test Circuit and Waveforms CLOCK ENABLE RESET MC14518B MC14520B Q2 Q3 MC14518B, MC14520B 20 ns CLOCK INPUT ...

  • Page 6

    ... RESET ENABLE CLOCK Figure 4. Decade Counter (MC14518B) Logic Diagram RESET ENABLE CLOCK Figure 5. Binary Counter (MC14520B) Logic Diagram MC14518B, MC14520B (1/2 of Device Shown (1/2 of Device Shown) http://onsemi.com 6 Q2 ...

  • Page 7

    ... MC14520BDW MC14520BDWG MC14520BDWR2 MC14520BDWR2G MC14520BFEL MC14520BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC14518B, MC14520B Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOIC− ...

  • Page 8

    ... B 16X 0. SEATING PLANE e 14X T MC14518B, MC14520B PACKAGE DIMENSIONS PDIP−16 P SUFFIX PLASTIC DIP PACKAGE CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS 4. DIMENSION B DOES NOT INCLUDE 5. ROUNDED CORNERS OPTIONAL. L SEATING ...

  • Page 9

    ... Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com MC14518B, MC14520B PACKAGE DIMENSIONS SOEIAJ−16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966− ...