MC14569B ON Semiconductor, MC14569B Datasheet - Page 6

• Manufacturer Part Number: MC14569B
• Description: Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
• Manufacturer: ON Semiconductor

INPUTS
Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
each positive transition of this signal.
OUTPUTS
goes high for one clock cycle when the counter has
decremented to zero.
significant counter. This output will be inactive unless the
preset input P7 has been set high.
4–bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs.
Clock (Pin 9) — Preset data is decremented by one on
Zero Detect (Pin 1) — This output is normally low and
Q (Pin 15) — Output of the last stage of the most
The MC14569B is a programmable divide–by–N dual
The divide ratio N (N being the value programmed on the
8.0
6.0
4.0
2.0
18
16
14
12
10
0
– 40
– 20
OPERATING CHARACTERISTICS
1
and CTL
T
A
0
, AMBIENT TEMPERATURE ( C)
PIN DESCRIPTIONS
http://onsemi.com
2
MC14569B
.
+ 20
6
+ 40
CONTROLS
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
the least significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
usually connected to ground.
connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to “0”, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to V
Cascade Feedback (Pin 7) — This pin is normally set
CTL
CTL
V
V
When cascading the MC14569B to the MC14526B, the
SS
DD
+ 60
(Pin 18) — Negative Supply Voltage. This pin is
1
2
(Pin 16) — Positive Supply Voltage. This pin is
(Pin 10) — This pin controls the counting mode of
(Pin 2) — This pin controls the counting mode of
C
V
L
DD
+ 80
= 50 pF
= 15 V
5.0 V
10 V
+ 100
DD
.