RC28F256J3F95 Numonyx, RC28F256J3F95 Datasheet
RC28F256J3F95
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RC28F256J3F95 Summary of contents
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... Numonyx 64 OTP bits, available for customer programming Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend — Numonyx™ Flash Data Integrator (FDI) — Common Flash Interface (CFI) Compatible Packaging — 56-Lead TSOP — 64-Ball Easy BGA package Datasheet ...
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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the Numonyx website at http://www.numonyx.com. ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Contents 1.0 Functional Overview .................................................................................................. 5 1.1 Document purpose .............................................................................................. 5 1.2 Product overview................................................................................................. 5 1.3 Configuration & Memory Map ................................................................................ 7 1.4 Device ID ........................................................................................................... 8 2.0 Package Information ................................................................................................. 9 2.1 56-Lead TSOP Package, 256-Mbit .......................................................................... 9 2.2 Easy BGA Package, 256-Mbit .............................................................................. 11 3.0 Ballout..................................................................................................................... 12 3.1 Easy BGA Ballout, 256-Mbit ................................................................................ 12 3.2 56-Lead TSOP Package Pinout, 256-Mbit .............................................................. 13 4.0 Signal Descriptions .................................................................................................. 14 5 ...
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... Program and erase characteristics ...........................................................................48 16.1 Program & Erase Specifications............................................................................48 17.0 Ordering Information...............................................................................................49 A Reference Information .............................................................................................50 A.1 Common Flash Interface .....................................................................................50 A.2 Query Structure Output ......................................................................................50 A.3 Flow Charts.......................................................................................................57 B Terms, definitions, and acronyms ............................................................................62 B.1 Nomenclature....................................................................................................62 B.2 Acronyms .........................................................................................................62 B.3 Conventions......................................................................................................63 C Revision History.......................................................................................................64 Datasheet 4 ® Numonyx™ StrataFlash Embedded Memory (J3-65nm) December 2008 319942-02 ...
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... The Numonyx™ StrataFlash mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Numonyx 65 nm ETOX™ X process technology. Offered in 32-Mbit up through 256-Mbit densities, the Numonyx™ Embedded Memory (J3-65nm) device brings reliable, low-voltage capability (3 V read, program, and erase) with high speed, low-power operation. The Numonyx™ ...
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... Likewise, the device has a wake time (t RP#-high until writes to the CUI are recognized. With RP the Status Register is cleared. Datasheet 6 Numonyx™ StrataFlash Table 6, “Chip Enable Truth Table for 256-Mb” on and RP the standby mode is enabled. When RP ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 1.3 Configuration & Memory Map The J3-65nm device features a symmetrically-blocked architecture. The flash device main array is divided as follows: • 256-Mbit, organized into two-hundred-fifty-six 128-Kbyte blocks. Figure 1: J3-65nm Memory Map A<24:0> 256 Mbit 1FFFFFF 128-Kbyte Block 1FE0000 ...
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... Device ID Table 1: Device Identifier Codes Code Device Code Datasheet 8 Numonyx™ StrataFlash Address 256-Mbit 00001h ® Embedded Memory (J3-65nm) Data 001Dh December 2008 319942-02 ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 2.0 Package Information 2.1 56-Lead TSOP Package, 256-Mbit Figure 2: 56-Lead TSOP Package Mechanical Z Pin 1 See Detail A Detail A Notes: 1. One dimple on package denotes Pin two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. ...
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... Table 2: 56-Lead TSOP Dimension Table Parameter Symbol Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset Datasheet 10 Numonyx™ StrataFlash Millimeters Min Nom D 19.800 20.00 L 0.500 0.600 N 56 θ 0° 3° 0.150 0.250 ® ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 2.2 Easy BGA Package, 256-Mbit Figure 3: Easy BGA Mechanical Specifications Ball A1 D Corner Top View - Plastic Backside Complete Ink Mark Not Shown A1 A2 Table 3: Easy BGA Package Dimensions Table ...
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... DQ9 DQ3 F BYTE# DQ0 DQ10 DQ11 G A23 A0 DQ2 VCCQ H CE2 RFU VCC VSS Easy BGA Top View – Ball Side Down Datasheet 12 Numonyx™ StrataFlash A13 VCC A18 A22 A22 A18 A14 RFU A19 CE1 CE1 A19 A15 ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 3.2 56-Lead TSOP Package Pinout, 256-Mbit Figure 5: 56-Lead TSOP Package Pinout (256 Mbit ( ...
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... GND/VSS Supply GROUND: Ground reference for device logic voltages. Connect to system ground. NC — No Connect: Lead is not internally connected; it may be driven or floated. Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device RFU — functionality and enhancement. Datasheet 14 Numonyx™ StrataFlash Name and Function Table 6, “ ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 5.0 Bus Interface This section provides an overview of Bus operations. There are three operations flash memory: Read, Program (Write), and Erase. CE[2:0]-enable, OE#-low, WE#-high and RP#-high enable device read operations. Addresses are always assumed to be valid. OE#-low activates the outputs and gates selected data onto the I/O bus ...
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... OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes. Datasheet 16 ® Numonyx™ StrataFlash Embedded Memory (J3-65nm) Table 6 on page 21. 15). Standard microprocessor write timings are used. ), the device outputs are disabled. ...
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... Lock-Bit Configuration modes CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Numonyx Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... Suspend 0xD0 Suspend Resume Datasheet 18 Numonyx™ StrataFlash Table 7 shows valid device command codes and Description Places the device in Read Array mode. Array data is output on DQ[15:0]. Places the device in Read Status Register mode. The device enters this mode after a program or erase command is issued. SR data is output on DQ[7:0]. ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Table 7: Command Codes and Definitions (Sheet Mode Code Device Mode 0x60 Block lock Setup 0x01 Block lock 0xD0 Unlock Block Protection program 0xC0 setup Extended Function 0xEB Interface (EFI) B8h Configuration Set-Up 00h ...
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... Datasheet 20 Numonyx™ StrataFlash First Bus Cycle Second Bus Cycle Bus Cycles ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 7.0 Read operation The device can be in any of four read states: Read Array, Read Identifier, Read Status Register or Read Query. Upon power-up, or after a reset, the device defaults to Read Array mode. To change the read state, the appropriate read command must be written to the device (see sections describe read-mode operations in detail ...
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... Factory-Programmed OTP register 64-bit User-Programmable OTP Register Notes: 1. BBA = Block Base Address. 2. DBA = Device base Address, Numonyx reserves other configuration address locations not used in either x8 or x16 modes during manufacturer and device ID reads. The lowest order 0 address line ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Issuing the CFI Query command places the device in CFI Query mode. Subsequent reads output CFI information on DQ[15:0]. The device remains in CFI Query mode until a different read command is issued program or erase operation is performed, which changes the read mode to Read Status Register mode. ...
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... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Datasheet 24 Numonyx™ StrataFlash Figure 19, “Buffer Program Flowchart” on page ® Embedded Memory (J3-65nm) 59). ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Programming Confirm command is written to the device, a command sequence error occurs and SR[7,5,4] are set error occurs while writing to the array, the device stops programming, and SR[7,4] are set, indicating a programming failure. When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence ...
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... Register error bit(s). Also, asserting RP# aborts suspended block-erase and programming operations, rendering array contents at the addressed location(s) indeterminate. Datasheet 26 Numonyx™ StrataFlash Section 8.0, “Program operation”). Erasing is performed on a Figure 21, “Block Erase Flowchart” on page Table 8 shows the Suspend and Resume command bus- ® ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) To suspend an on-going erase or program operation, issue the Suspend command to any device address. The program or erase operation suspends at pre-determined points during the operation after a delay of t mode) goes high, SR[7, (erase-suspend) or SR[7, (program-suspend). Note: Issuing the Suspend command does not change the read mode of the device. The ...
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... Normal Block Locking J3-65nm has the unique capability of Flexible Block Locking (locked blocks remain locked upon reset or power cycle): All blocks are unlocked at Numonyx factory. Blocks can be locked individually by issuing the Set Block Lock Bit command sequence to any address within a block. Once locked, blocks remain locked when power is removed, or ...
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... Password Access may be combined with Non-Volatile Protection and/or Volatile Protection to create a multi- tiered solution. Please contact your Numonyx Sales for further details concerning Password Access. December 2008 319942-02 Datasheet ...
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... Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status Datasheet 30 Numonyx™ StrataFlash PEN Program Prog/Erase Status ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 11.1.1 Clearing the Status Register The Clear Status Register command clears the status register. It functions independent of VPEN. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity ...
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... CPU or ASIC, hence preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments: • One segment is programmed at the Numonyx factory with a unique unalterable 64- bit number. • The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming ...
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... The user-programmable segment of the PR is lockable by programming Bit 1 of the Protection Lock Register (PLR Bit 0 of this location is programmed the Numonyx factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the Protection Register ...
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... User 1 B User 1 C User 1 D User 1 E User 1 F User 1 Note: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX: Datasheet 34 Numonyx™ StrataFlash ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 12.0 Power and Reset Specifications 12.1 Power-Up and Power-Down Power supply sequencing is not required if VPEN is connected to VCC or VCCQ. Otherwise VCC and VCCQ should attain their minimum operating voltage before applying VPEN. Power supply transitions should only occur when RP# is low. This protects the device from accidental programming or erasure during power transitions ...
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... Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high Datasheet 36 Numonyx™ StrataFlash Parameter is < t Min, but this is not guaranteed. PLPH VCCPH V IH RST# [ ...
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... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx MLC flash memory devices draw their power from VCC, VSS, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...
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... These are stress ratings only. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design. Table 17: Absolute Maximum Ratings ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 14.0 Electrical characteristics 14.1 DC Current Specifications Please refer to Figure 6, “Chip Enable Truth Table for 256-Mb” on page 15 understand the device is disable or enabled. Table 19: DC Current Characteristics Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current ...
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... Address, Data, C Input Capacitance CE#, WE#, OE Output Capacitance OUT Notes: 1. Capacitance values are for a single die. 2. Sampled, not 100% tested. 3. Silicon die capacitance only, add 1 pF for discrete packages. Datasheet 40 Numonyx™ StrataFlash 2.7 - 3.6 V Min –0.5 2.0 — — 0.85 × V CCQ V – CCQ 0.2 — 2.7 1.5 ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 15.0 AC characteristics Timing symbols used in the timing diagrams within this document conform to the following convention Figure 8: Timing Signal Naming Convention Source Signal Source State Figure 9: Timing Signal Name Decoder Signal Address A Data - Read Q Data - Write ...
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... Test configuration component value for worst case speed conditions includes jig capacitance L . Table 22: Test Configuration Component Value for Worst Case Speed Conditions Test Configuration VCCQ Min Standard Test Datasheet 42 Numonyx™ StrataFlash Device Under Test C L ® Embedded Memory (J3-65nm) Out C (pF) L ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) 15.2 AC Read Specifications Chip enable truth table can be found on Test configuration can be found in Table 23: AC Read Specification Nbr. Symbol Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to Output Delay AVQV Output Delay X ELQV ...
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... CE low is defined as the falling edge of CE0, CE1, or CE2 that enables the device CE0, CE1, or CE2 that disables the device this diagram, BYTE# is asserted high. Datasheet 44 Numonyx™ StrataFlash R16 R12 R13 (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads, ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Figure 14: 16-Word Asynchronous Page Mode Read A[MAX:5][A] A[4:1][A] CEx[E] OE#[G] WE#[W] DQ[15:0][Q] R5 RP#[P] BYTE# Notes low is defined as the falling edge of CE0, CE1, or CE2 that enables the device CE0, CE1, or CE2 that disables the device this diagram, BYTE# is asserted high. ...
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... For array access required in addition to t AVQV 7. STS timings are based on STS configured in its RY/BY# default mode should be held at V PEN PENH = 0). Datasheet 46 Numonyx™ StrataFlash Table 6 on page 15 Parameter ) Going Low X ) Going Low X ) Going High X ) Going High X ) High X ) High ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Figure 15: Asynchronous Write Waveform ADDRESS [A] CEx (WE#) [E (W)] WE# (CEx) [W (E)] OE# [G] DATA [D/Q] STS[R] W1 RP# [P] VPEN [V] Figure 16: Asynchronous Write to Read Waveform Address [A] CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RST#/ RP# [P] VPEN [V] December 2008 319942- W11 ...
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... ERS/SUSP command W600 t Program suspend time SUSP/P W601 t Erase suspend time SUSP/E Notes: 1. Does not apply when in Byte Mode (Byte# at VIL) Datasheet 48 Numonyx™ StrataFlash = +25 °C and nominal voltages A Parameter Typ 150 176 216 272 396 700 0.8 — ® Embedded Memory (J3-65nm) ...
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... RC = 64-Ball Easy BGA PC = 64-Ball Pb-Free Easy BGA Product line designator TM 28F = Numonyx Flash Memory Device Density 256 = x8/x16 (256 Mbit) Table 26: Valid Combinations 256-Mbit TE28F256J3F105 JS28F256J3F105 PC28F256J3F95 RC28F256J3F95 December 2008 319942-02 Access Speed 95 ns 105 ns Lithography Product Family TM ® Numonyx StrataFlash ...
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... Table 27: Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses x16 device 10h x16 mode x16 device Datasheet 50 Numonyx™ StrataFlash Query data with maximum device bus width addressing Hex ASCII Hex Code Offset Value 10: 0051 “Q” 11: 0052 “ ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Table 27: Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses (1) x8 mode N/A Note: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is " ...
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... BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is 128 Kbyte). 3. Offset 15 defines “P” which points to the Primary Numonyx-Specific Extended Query Table. A.2.2 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) A.2.4 System Interface Information The following device information can optimize system interface software. Table 32: System Interface Information Offset Length V logic supply minimum program/erase voltage CC 1Bh 1 bits 0–3 BCD 100 mV bits 4–7 BCD volts V logic supply maximum program/erase voltage ...
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... Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported bit9 Simultaneous Operation Supported bit 30 CFI Link(s) to follow (256 Mb) bit 31 Another “Optional Feature” field to follow Datasheet 54 Numonyx™ StrataFlash Description ® Embedded Memory (J3-65nm) Hex Value Add. Code ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Table 35: Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (Optional Flash Features and Commands) Supported functions after suspend: read Array, Status, Query Other supported operations are: (P+9)h 1 bits 1–7 reserved; undefined bits are “0” ...
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... J3C mark for VIL fix for customers Note: 1. The variable pointer which is defined at CFI offset 15h. Datasheet 56 Numonyx™ StrataFlash Description (Optional Flash Features and Commands) n HEX value represents the number of read- n+1 HEX value represents the maximum ® Embedded Memory (J3-65nm) Hex Add ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) A.3 Flow Charts Figure 18: Program/Erase Suspend/Resume Flowchart Start Command Cycle - Issue Suspend Command - Address = any device address - Data = 0xB0 Wait t SUSP Read Status Register See Status Register Flowchart Erase Suspended ? (SR.6 = '1') No Program Suspended ? (SR.2 = '1') No Any Errors ? ...
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... Datasheet 58 ® Numonyx™ StrataFlash Embedded Memory (J3-65nm) December 2008 319942-02 ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Figure 19: Buffer Program Flowchart Start Device Use Single Word Supports Buffer No Programming Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read Status Register (at Block Address) Is WSM Ready? SR ...
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... Issue Block Lock Setup Command - Address = block address - Data = 0x60 - Issue Lock/Unlock Command - Address = block address - Data = 0x01 (Lock Block) -or- Error Handler User-Defined Routine Datasheet 60 Numonyx™ StrataFlash Start Command Cycle Data Cycle 0xD0 (Unlock Block) Read Status Register See Status Register Flowchart Yes No Errors ? ® ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Figure 21: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase confirm (0xD0) Check Ready Status - Read Status Register Command not required - Perform read operation - Read Ready Status on signal SR ...
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... Figure 22: OTP Register Programming Flowchart Datasheet 62 ® Numonyx™ StrataFlash Embedded Memory (J3-65nm) Start OTP Program Setup - Write 0xC0 - OTP Address Confirm Data - Write OTP Address and Data Check Ready Status - Read Status Register Command not required - Perform read operation - Read Ready Status on signal SR ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) Figure 23: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear Status Register Command December 2008 319942-02 Start Command Cycle ...
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... Write State Machine CFI Common Flash Interface FDI Flash Data Integrator MLC Multi-Level Cell SBC Single Bit Cell NC Not Connect DU Don’t Use Datasheet 64 Numonyx™ StrataFlash AMIN = A0 for x8 AMIN = A1 for x16 AMAX = A24 ® Embedded Memory (J3-65nm) December 2008 319942-02 ...
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... Numonyx™ StrataFlash Embedded Memory (J3-65nm) B.3 Conventions h: Hexadecimal Suffix k (noun): 1,000 M (noun): 1,000,000 Bit: 1 bit Nibble: 4 bits Byte: 8 bits Word: 16 bits KByte: 1,024 bytes Kword: 1,024 words Kb: 1,024 bits KB: 1,024 bytes Mb: 1,048,576 bits MB: 1,048,576 bytes Brackets: Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i ...
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... Appendix C Revision History Date Revision Description May 2008 01 Initial release December 2008 02 For 256-Mbit J3-65nm release Datasheet 66 ® Numonyx™ StrataFlash Embedded Memory (J3-65nm) December 2008 319942-02 ...