BR31P PulseCore Semiconductor, BR31P Datasheet - Page 3

• Manufacturer Part Number: BR31P
• Description: 5-pin ?p Voltage Supervisor With Manual Reset
• Manufacturer: PulseCore Semiconductor

NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, PCS811 series are
relatively resistant to short-duration negative-going VCC
transient.
ENSURING A VALID RESET OUTPUT DOWN TO
VCC=0
longer sinks current; it becomes an open circuit. In this
case, high-impedance CMOS logic inputs connecting to
RESET can drift to undetermined voltages. Therefore,
PCS811/812 with CMOS is perfect for most applications of
VCC below 0.9V. However in applications where RESET
January 2007
rev 0.1
DETAIL DESCRIPTION
RESET OUTPUT
µP will be activated at a valid reset state. These µP
supervisory circuits assert reset to prevent code execution
errors
conditions.
RESET
V
an internal timer keeps RESET low for the reset timeout
period; after this interval, RESET goes high.
MANUAL RESET INPUT
allowing operators, test technicians, or external logic
circuitry to initiate a reset. Logic low on MR asserts reset.
Reset will remain asserted for the Reset Active Timeout
Period (t
internal 20KΩ pull-up resistor, so it can be floating if it is
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Another
alternative is to connect a normal switch from MR to GND
to create a manual reset function. Connecting a 0.1µF
capacitor from MR to ground can provide noise immunity
APPLICATION INFORMATION
When VCC falls below 0.9V, PCS811 RESET output no
Many µP-based products require manual reset capability,
TH
>VCC>0.9V. Once VCC exceeds the reset threshold,
during
RP
is
) after MR returns high. This input has an
guaranteed
power-up,
to
power-down,
5-Pin
be
Notice: The information in this document is subject to change without notice.
a
µP Voltage Supervisor with Manual Reset
logic
or
brownout
low
for
must be valid down to 0V, adding a pull-down resistor to
RESET causes any leakage currents to flow to ground,
holding RESET low.
If a brownout condition occurs (VCC drops below the reset
threshold), RESET goes low. Any time VCC goes below
the reset threshold, the internal timer resets to zero, and
RESET goes low. The internal timer is activated after VCC
returns above the reset threshold, and RESET remains
low for the reset timeout period.
The manual reset input (MR) can also initiate a reset.
PCS812 has an active-high RESET output that is the
inverse of PCS811’s RESET
output.
to prevent noise caused by long cables of MR or noisy
environment.
BENEFITS
THRESHOLD
3V±10% are ideal for systems using a 5V±5% or 3V±5%
power supply. The reset is guaranteed to assert after the
power supply falls out of regulation, but before power
drops below the minimum specified operating voltage
range of the system ICs. The pre-trimmed thresholds are
reducing the range over which an undesirable reset may
occur.
PINS
PCS811/812 reset outputs. If PCS811 RESET output is
asserted high and the µP wants to pull it low,
indeterminate logic levels may occur. To correct such
cases, connect a resistor between PCS811 RESET (or
PCS812 RESET) output and the µP reset I/O. Buffer the
reset output to other system components.
PCS811/812 with specified voltage as 5V±10% or
INTERFACING TO µP WITH BIDIRECTIONAL RESET
µPs with bidirectional reset pins can contend with
OF
HIGHLY
PCS811/PCS812
output.PCS811’s RESET
ACCURATE
3 of 8
RESET