ST16C550 Exar Corporation, ST16C550 Datasheet
ST16C550
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ST16C550 Summary of contents
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... The ST16C550 provides internal loop- back capability for on board diagnostic testing. The ST16C550 is available in 40 pin PDIP, 44 pin PLCC, and 48 pin TQFP packages fabricated in an advanced CMOS process to achieve low drain power and high speed requirements ...
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... ST16C550 Figure 1, PACKAGE DESCRIPTION, ST16C550 48 Pin TQFP Package N. RCLK 5 N.C. 6 ST16C550CQ48 CS0 10 CS1 -CS2 11 12 -BAUDOUT Rev. 4.30 40 Pin DIP Package N. RESET -OP1 -DTR D6 7 -RTS -OP2 31 RCLK 9 30 ...
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... Figure 2, BLOCK DIAGRAM D0-D7 -IOR,IOR -IOW,IOW RESET A0-A2 -AS CS0,CS1 -CS2 -DDIS INT -RXRDY -TXRDY Rev. 4.30 ST16C550 Transmit Transmit FIFO Shift Registers Register Receive Receive FIFO Shift Registers Register Modem Control Clock Logic & Baud Rate Generator -DTR,-RTS -OP1,-OP2 -CTS -RI -CD ...
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... I Write data strobe. Its function is the same as -IOW (see - IOW), but it acts as an active high input signal. Either -IOW or IOW is required to transfer data from the CPU to ST16C550 during a write operation. Connect to logic 0 when using -IOW Address Strobe. A logic 1 transition on -AS latches the state of the chip selects and the register select bits, A0-A2 ...
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... I Read data strobe (active low strobe). A logic 0 on this pin transfers the contents of the ST16C550 data bus to the CPU. Connect to logic 1 when using IOR Write data strobe (active low strobe). A logic 0 on this pin transfers the contents of the CPU data bus to the addressed internal register ...
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... Pin Description 48 type 22 O Drive Disable. This pin goes to a logic 0 when the external CPU is reading data from the ST16C550. This signal can be used to disable external transceivers or other logic func- tions Output-1 (User Defined) - See bit-2 of modem control register (MCR bit-2). ...
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... UART’s transmit or receive operation Receive Data - This pin provides the serial receive data input to the ST16C550. A logic 1 indicates no data or an idle channel. During the local loop-back mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally, see figure 12. ...
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... CMOS process. The ST16C550 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The ST16C550 is designed to work with high speed modems and shared network environments, that require fast data process- ing time. Increased performance is realized in the ST16C550 by the larger transmit and receive FIFO’ ...
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... Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch In this case the ST16C550 FIFO may hold more char- acters than the programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit- 0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty ...
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... The programmable Baud Rate Generator is capable of accepting an input clock MHz, as required for supporting a 1.5Mbps data rate. The ST16C550 can be configured for internal or external clock operation. Divisor (in decimal) = (XTAL1 clock frequency) / (serial data rate x 16) Table 3, BAUD RATE GENERATOR PROGRAMMING TABLE (1 ...
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... DMA Operation The ST16C550 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFO’s in the DMA mode (FCR bit-3). The DMA mode affects the state of the -RXRDY and -TXRDY output pins. The ...
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... ST16C550 Figure 4, INTERNAL LOOP-BACK MODE DIAGRAM -IO R ,IO R - Rev. 4. ift R eg isters R eg ister ...
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... REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 4, ST16C550 INTERNAL REGISTERS Register BIT-7 [Default] Note *2 General Register Set ...
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... IER Vs Receive/Transmit FIFO Polled Mode Op- eration When FCR BIT-0 equals a logic 1; resetting IER bits 0-3 enables the ST16C550 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... Transmit operation in mode “1”: When the ST16C550 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty ...
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... ST16C550 Interrupt Status Register (ISR) The ST16C550 provides four levels of prioritized inter- rupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. Rev. 4.30 ST16C550 BIT-2 Word length (Bit time(s)) 0 5,6,7 6,7,8 LCR BIT-3: Parity or no parity can be selected via this bit. ...
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... Rev. 4.30 MCR BIT 5-7: Not used and set to “0”. Line Status Register (LSR) This register provides the status of data transfers between. the ST16C550 and the CPU. LSR BIT-0: Logic data in receive holding register or FIFO. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register or FIFO ...
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... Status Interrupt will be generated. Rev. 4.30 ST16C550 MSR BIT-2: Logic -RI Change (normal default condition) Logic 1 = The -RI input to the ST16C550 has changed from a logic logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic -CD Change (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read ...
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... ST16C550 ST16C550 EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER IER BITS 0-7 = logic 0 ISR ISR BIT-0=1, ISR BITS 1-7 = logic 0 LCR, MCR BITS 0-7 = logic 0 LSR LSR BITS 0-4 = logic 0, LSR BITS 5-6 = logic 1 LSR, BIT 7 = logic 0 MSR MSR BITS 0-3 = logic 0, MSR BITS 4-7 = logic levels of the ...
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... Delay from -IOR to reset -RxRdy 26d T Delay from -IOW to set -TxRdy 27d T Delay from start to reset -TxRdy 28d T Reset pulse width R N Baud rate devisor Note 1: Applicable only when -AS is tied low. Rev. 4.30 ST16C550 Limits Limits Units 3.3 5.0 Min Max Min Max ...
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... ST16C550 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter V Clock input low level ILCK V Clock input high level ...
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... T2w EXTERNAL CLOCK -BAUDOUT 1/2 -BAUDOUT 1/3 -BAUDOUT 1/3> -BAUDOUT Rev. 4.30 T1w T3w Clock timing 23 ST16C550 X450-CK-1 ...
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... ST16C550 - General Read Timing when using -AS signal T4w -AS T5s A0-A2 Address T6s -CS2 CS1-CS0 T13d ...
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... ctive T 12h D ata V a lid ctive ctive ST16C550 V alid A ddress T 7h ctive T 12h T 12d V a lid ctive ...
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... ST16C550 -IOW Active IOW -RTS Change of state -DTR -CD -CTS -DSR INT -IOR IOR -RI Rev. 4.30 T17d Change of state Change of state T18d Active T19d Active Modem input/output timing 26 Change of state T18d Active Active Active Active T18d Change of state X450-MD-1 ...
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... START BIT RX INT -IOR IOR Rev. 4.30 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Receive timing 27 ST16C550 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T20d Active T21d X450-RX-1 ...
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... ST16C550 START BIT RX -RXRDY -IOR IOR Receive ready timing in non FIFO mode Rev. 4.30 DATA BITS (5- STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T25d Active Data Ready T26d Active X550-RX-2 ...
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... START BIT RX -RXRDY -IOR IOR Receive ready timing in FIFO mode Rev. 4.30 DATA BITS (5- ST16C550 STOP BIT D6 D7 PARITY First byte BIT that reaches the trigger level T25d Active Data Ready T26d Active X550-RX-3 ...
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... ST16C550 22d ctive -IO W Rev. 4. (5- BIT BIT BIT S A ctive eady T 23d Transmit timing ...
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... START BIT TX -IOW Active IOW BYTE #1 -TXRDY Transmit ready timing in non FIFO mode Rev. 4.30 DATA BITS (5- T27d Active Transmitter ready 31 ST16C550 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T28d Transmitter not ready X550-TX-2 ...
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... ST16C550 START BIT TX -IOW Active IOW D0-D7 BYTE #16 T27d -TXRDY Transmit ready timing in FIFO mode Rev. 4.30 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T28d FIFO Full 32 STOP BIT D6 D7 PARITY BIT X550-TX-3 ...
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... MAX MIN 0.165 0.180 4.19 0.090 0.120 2.29 0.020 ----- 0.51 0.013 0.021 0.33 0.026 0.032 0.66 0.008 0.013 0.19 0.685 0.695 17.40 0.650 0.656 16.51 0.590 0.630 14.99 0.500 typ 12.70 typ 0.50 BSC 1.27BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 33 ST16C550 C Seating Plane MAX 4.57 3.05 ------ 0.53 0.81 0.32 17.65 16.66 16.00 1.42 1.22 1.14 ...
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... ST16C550 PACKAGE OUTLINE DRAWING Seating Plane A 1 Note: The control dimension is the millimeter column SYMBOL Rev. 4.30 48 LEAD THIN QUAD FLAT PACK (TQFP INCHES MILLIMETERS MIN MAX MIN A 0.039 0.047 1.00 A 0.002 0.006 0. 0.037 0.041 ...
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... EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet September 2003 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 4.30 ST16C550 CHANGES NOTICE 35 DATE Sept 2003 ...