HT0313A Tomato LSI, Inc., HT0313A Datasheet - Page 19

• Manufacturer Part Number: HT0313A
• Description: 65COM/132SEG DRIVER & CONTROLLER FOR STN LCD
• Manufacturer: Tomato LSI, Inc.

HT0313A
TOMATO LSI Inc.
6-2. DISPLAY DATA RAM (DDRAM)
a.
The DDRAM stores pixel data for the LCD. It has 65-row (8 page x 8 bit + 1) by 132-column addressable
array. Each pixel can be selected by specifying the page and the column address. The 65 rows are
divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written
to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the MPU
correspond to the LCD common direction as shown in Figure 6-4.
The MPU can read from and write to DDRAM through the I/O buffer, which is independent operation from
signal reading for the LCD driver. This independent operation makes it possible that the MPU writes the
data into the DDRAM at the same time as data is being displayed without causing the LCD flicker.
b. Page address circuit
This circuit is for providing a page address to DDRAM shown in figure 6-6. The 4-bit page address
register changed by only the “Set page” instruction. Page address 8 (DB3, DB2, DB1, DB0 = 1, 0, 0, 0) is
a special RAM area for the icons and display data DB0 is only valid.
c. Column address circuit
Column address circuit has a 8-bit preset counter that provides column address to the DDRAM as shown
in figure 6-6. When the “Set column address MSB / LSB” instruction is issued, 8-bit [Y7:Y0] is updated.
And this address is increased by +1 each display data Read/Write instruction. This allows that the MPU
display data can be accessed continuously. The increment of the column address stops with 83H. And
the counter is not increased and locked if the address is specified over 84H. It is unlocked if a column
address is set again by “Set column address MSB / LSB” instruction. The column address counter is
independent of the page address register.
The ADC select instruction makes it possible to convert the relationship between the column address and
the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing the ADC
select instruction. Refer to the figure 6-5.
DDRAM
DB0
DB1
DB2
DB3
DB4
Display data RAM
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
0
1
1
0
1
1
0
1
0
1
19
1
0
1
1
0
……
……
……
……
……
Figure 6-4. RAM-to-LCD data transfer
0
1
0
1
0
LCD display
COM0
COM1
COM2
COM3
COM4
……
……
……
……
……
Ver 0.0