UCC1858 Unitrode Semiconductor, UCC1858 Datasheet - Page 8

• Manufacturer Part Number: UCC1858
• Description: High Efficiency, High Power Factor Preregulator
• Manufacturer: Unitrode Semiconductor

APPLICATION INFORMATION (cont.)
current or the capacitor life can be increased as a result.
In cost sensitive designs where hold-up time is not criti-
cal, this is a significant advantage.
An alternative method of synchronization to achieve the
same ripple reduction is possible. In this method, the
turn-on of Q1 is synchronized to the turn-off of Q2. While
this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters,
the synchronization is much more difficult to achieve and
the circuit can become susceptible to noise as the syn-
chronizing edge itself is being modulated.
Reference Signal (I
Like the UC3854 series, the UCC3858 has an Analog
Computation Unit (ACU) which generates a reference
current signal for the current error amplifier. The inputs to
the ACU are (signals proportional to) instantaneous line
voltage, input voltage RMS information and the voltage
error amplifier output. Unlike prior techniques of RMS
voltage sensing, UCC3858 employs a patent pending
technique to simplify the RMS voltage generation and
eliminate performance degradation caused by the prior
techniques. With the novel technique (shown in Figure 6),
need for external two pole filter for V
eliminated. Instead, the IAC current is mirrored and used
to charge an external capacitor (C
cle. The voltage on C
shape and is given by equation 3. At the end of the half-
cycle, C
digital word for further processing in the ACU. C
discharged and readied for integration during the next
half cycle. The advantage of this method is that the sec-
ond harmonic ripple on the V
Figure 6. Novel Circuit for RMS Signal Generation
RMS
voltage is held and converted into a 4-bit
MULT
RMS
) Generation
takes the integrated sinusoidal
RMS
signal is virtually elimi-
RMS
RMS
) during a half cy-
generation is
UDG-97124
RMS
is
8
nated. Such second harmonic ripple is unavoidable with
the limited roll-off of a conventional 2-pole filter and re-
sults in a 3rd harmonic distortion in the input current sig-
nal. The dynamic response to the input line variations is
also improved as a new V
cycle.
For proper operation, I
100 A at peak line voltage. For universal input voltage
with peak value of 265 V
noise sensitivity of the IC requires a small bypass capaci-
tor for high frequency noise filtering. The value of this ca-
pacitor should be limited to 330pF maximum. The V
value should be approximately 1V at the peak of low line
(80 VAC) to minimize any digitization errors. The peak
value of V
sired C
for 50Hz line and 75nF for 60Hz line.
The multiplier output current is given by equation (4) with
K=0.4.
The multiplier peak current is limited to 200 A and the
selected values for IAC and V
the current is within this range. Another limitation of the
multiplier is that Imult can not exceed two times the IAC
current, limiting the minimum voltage on V
The discrete nature of the RMS voltage feedforward
means that there are regions of operation where the input
voltage changes, but the V
plier does not change. The voltage error amplifier com-
pensates for this by changing its output to maintain the
required multiplier output current. When the output of the
ADC changes, there is a jump in the output of the error
amplifier. There is a resultant shift in the foldback fre-
quency if the converter is at light load. However, the im-
pact of this change is minimal on the overall converter
operation.
Another key consideration with the RMS voltage scheme
is that it relies on the zero-crossing of the IAC signal to
be effective. At very light loads and high line conditions,
the rectified AC does not quite reach zero if a large ca-
pacitor is being used for filtering on the rectified side of
the bridge. In such instances, the feedforward effect does
not take place and the controller functionality is lost. For
UCC3858, the I
zero crossing detection to take place. It is recommended
that the capacitor value be kept low enough for the light
RMS
V
I
MULT
CRMS
Crms
can be calculated from equation 3 to be 90nF
at high line then becomes 3.5V. The de-
AC
V
2
VAO
current should go below 10 A for the
I
ACpk
V
0.5
CRMS
ACpk
C
AC
RMS
RMS
, this means R
RMS
2
I
should be selected to be
AC
signal is generated every
CRMS
value fed into the multi-
1
K
COS
should ensure that
CRMS
AC
t
UCC1858
UCC2858
UCC3858
= 3.6M. The
.
CRMS
(3)
(4)