IDT82V2048S Integrated Device Technology, IDT82V2048S Datasheet
IDT82V2048S
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IDT82V2048S Summary of contents
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... CLK&Data Recovery Slicer Attenuator (DPLL) Digital Loopback Line Waveform Driver Shaper Attenuator Transmit All Ones Register Control Interface File Figure-1 Block Diagram 1 IDT82V2048S to +85 °C °C B8ZS/ Jitter HDB3/AMI Decoder IBLC Remote Detector Loopback AIS Detector B8ZS/ Jitter HDB3/AMI Encoder IBLC ...
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... A jitter attenuator is integrated in the IDT82V2048S and can be switched into either the transmit path or the receive path for all channels. The jitter attenuation performance meets ETSI CTR12/13, ITU G.736, G.742, G.823, and AT& ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RCLK TCLK RCLK TCLK RDP TDP RDP RDN TDN RDN VDDT VDDT VDDT VDDT TRING TTIP TRING GNDT GNDT GNDT GNDT ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED 1 PIN DESCRIPTION Table-1 Pin Description Pin No. Name Type TQFP144 TTIP0 45 TTIP1 52 TTIP2 57 TTIP3 64 TTIP4 117 TTIP5 124 TTIP6 129 TTIP7 136 Analog Output TRING0 46 TRING1 51 TRING2 58 TRING3 63 TRING4 118 TRING5 123 TRING6 130 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TD0/TDP0 37 TD1/TDP1 30 TD2/TDP2 80 TD3/TDP3 73 TD4/TDP4 108 TD5/TDP5 101 TD6/TDP6 8 TD7/TDP7 1 I BPVI0/TDN0 38 BPVI1/TDN1 31 BPVI2/TDN2 79 BPVI3/TDN3 72 BPVI4/TDN4 109 BPVI5/TDN5 102 BPVI6/TDN6 7 BPVI7/TDN7 144 TCLK0 36 TCLK1 29 TCLK2 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 RD0/RDP0 40 RD1/RDP1 33 RD2/RDP2 77 RD3/RDP3 70 RD4/RDP4 111 RD5/RDP5 104 RD6/RDP6 5 RD7/RDP7 O 142 CV0/RDN0 High-Z 41 CV1/RDN1 34 CV2/RDN2 76 CV3/RDN3 69 CV4/RDN4 112 CV5/RDN5 105 CV6/RDN6 4 CV7/RDN7 141 RCLK0 39 RCLK1 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 I MODE2 11 (Pulled to VDDIO/2) MODE1 I 43 MODE0/CODE CS/JAS 87 (Pulled to VDDIO/2) PBGA160 Hardware/Host Control Interface MODE2: Control Mode Select 2 The signal on this pin determines which control mode is selected to control the device: ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TS2/SCLK ALE/AS TS1/RD/R TS0/SDI/WR PBGA160 TS2: Template Select 2 In hardware control mode, the signal on this pin is the most significant bit for the transmit template select. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 SDO/RDY/ACK INT Open 82 Drain LP7/D7/AD7 28 LP6/D6/AD6 27 LP5/D5/AD5 I/O 26 LP4/D4/AD4 25 LP3/D3/AD3 24 LP2/D2/AD2 High-Z 23 LP1/D1/AD1 22 LP0/D0/AD0 21 PBGA160 SDO: Serial Data Output In serial host mode, the data is output on this pin ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 A4 12 MC3/A3 13 MC2/ MC1/A1 15 MC0/ 114 CLKE I 115 I TRST 95 Pull-up I TMS 96 Pull-up TCK I 97 PBGA160 MCn: Performance Monitor Configuration 3~0 In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one transmitter or receiver of channel for non-intrusive monitoring ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 O TDO 98 High-Z I TDI 99 Pull-up 17 VDDIO - 92 18 GNDIO - 91 VDDT0 44 VDDT1 53 VDDT2 56 VDDT3 65 - VDDT4 116 VDDT5 125 VDDT6 128 VDDT7 137 GNDT0 47 GNDT1 50 GNDT2 59 GNDT3 62 - GNDT4 119 ...
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... FUNCTIONAL DESCRIPTION 2.1 OVERVIEW The IDT82V2048S is a fully integrated octal short-haul line interface unit, which contains eight transmit and receive channels for use in either applications. The receiver performs clock and data recovery option, the raw sliced data (no retiming) can be output to the system ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RTIPn RRINGn Peak Detector TTIPn TRINGn Note: The grey blocks are bypassed and the dotted blocks are selectable. RTIPn RRINGn Peak Detector TTIPn TRINGn Note: The grey blocks are bypassed and the dotted blocks are selectable. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RTIPn RRINGn Peak Detector TTIPn TRINGn Table-2 System Interface Configuration (In Hardware Mode) Pin MCLK Clocked High (≥ 16 MCLK) Clocked High Low Table-3 System Interface Configuration (In Host Mode) Pin MCLK Pin TDNn CRSn in e-CRS ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 2.3 CLOCK EDGES The active edge of RCLKn and SCLK are selectable. If pin CLKE is high, the active edge of RCLKn is the rising edge, as for SCLK, that is falling edge. On the contrary, if CLKE is low, the active edge of RCLK is the falling edge and that of SCLK is rising edge ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-5 Configuration of the Line Code Rule Hardware Mode CODE Line Code Rule Low All channels in B8ZS/HDB3 High All channels in AMI Table-6 LOS Condition in Clock Recovery Mode Continuous Intervals LOS Differential Detected (1) Amplitude ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-8 Error Detection Hardware Mode Line Code Pin CVn Reports AMI Bipolar Violation Bipolar Violation + B8ZS/ Code Violation HDB3 + Excessive Zeros RCLKn RTIPn RRINGn RDn CVn RCLKn RTIPn 1 RRINGn 2 RDn CVn Line Code ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RCLKn RTIPn 2 RRINGn 1 3 RDn CVn 2.5 TRANSMITTER In transmit path, data in NRZ format are clocked into the device on TDn and encoded by AMI or B8ZS/HDB3 line code rules when single rail mode is configured or pre-encoded data in NRZ format are input on TDPn and TDNn when dual rail mode is configured ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-9 Built-in Waveform Template Selection TS2 TS1 TS0 Service Maximum cable loss at 772 kHz. 2.5.2 BIPOLAR VIOLATION INSERTION When configured in Single Rail Mode 2 with AMI line code enabled, pin TDNn/BPVIn is used as BPVI input ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION A R Line Line X NOTE: 1. Pulse T1124 transformer is recommended to be used in Standard (STD) operating temperature range (0°C to 70°C), while Pulse T1114 transformer is recommended to be used in Extended (EXT) operating temperature range is -40°C to +85°C. See Transformer Specifications Table for details ...
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... MCLK is clocked or high, setting bit RPDNn in register e-RPDN to ‘1’ will configure the corresponding receiver to be powered down. 2.16 INTERFACE WITH 5 V LOGIC The IDT82V2048S can interface directly with 5 V TTL family devices. The internal input pads are tolerant output from TTL and CMOS family devices. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 2.17.4 DUAL LOOPBACK Dual Loopback mode is set by setting bit DLBn in register DLB and bit RLBn in register RLB to ‘1’. In this configuration, after passing the encoder, the data and clock to be transmitted are looped back to decoder directly and output on RCLKn, RDn/RDPn and CVn/RDNn ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn Peak Detector TTIPn Driver TRINGn LOS Detector CLK&Data Jitter Slicer Recovery Attenuator (DPLL) Line Waveform Jitter Driver Shaper ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn TTIPn TRINGn 2.17.6 INBAND LOOPBACK Inband Loopback is a function that facilitates the system remote diagnosis. When this function is enabled, the chip will detect or generate the Inband Loopback Code. There are two kinds of Inband Loopback Code: Activate Code and Deactivate Code ...
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... Address/Command Byte SDO High Impedance 1. While R/W=1, read from IDT82V2048S; While R/W=0, write to IDT82V2048S. 2. Ignored. Figure-21 Serial Host Mode Timing data byte (D7~D0), as shown in Figure-21. When bit R/W is set to ‘1’, data is read out from pin SDO. When bit R/W is set to ‘0’, data on pin SDI is written into the register whose address is indicated by address bits A5~A1 ...
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... Pin INT is pulled high when there is no pending interrupt left. The interrupt handling in the interrupt service routine is showed in Figure-22. 2.20 G.772 MONITORING The eight channels of IDT82V2048S can all be configured to work as regular transceivers. In applications using only seven channels (chan- nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels’ ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RTIPn RRINGn TTIPn TRINGn G.772 Monitor RTIP0 RRING0 TTIP0 TRING0 LOS Detector CLK&Data Slicer Recovery (DPLL) Peak Detector Line Waveform Driver Shaper Transmit All Ones LOS Detector CLK&Data Slicer Recovery (DPLL) Peak ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 3 PROGRAMMING INFORMATION 3.1 REGISTER LIST AND MAP There are 23 primary registers (including an Address Pointer Control Register and 16 expanded registers in the device). Whatever the control interface is, 5 address bits are used to set the registers. In non-multiplexed parallel interface mode, the five dedicated address bits are A[4:0] ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-16 Expanded (Indirect Address Mode) Register List Address Hex Serial Interface A7-A1 Parallel Interface A7-A0 00 XX00000 01 XX00001 02 XX00010 03 XX00011 04 XX00100 05 XX00101 06 XX00110 07 XX00111 08 XX01000 09 XX01001 0A XX01010 0B XX01011 0C XX01100 0D XX01101 0E XX01110 0F XX01111 10 XX10000 11 XX10001 12 XX10010 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-17 Primary Register Map Address Register R/W Bit 7 Default 00H Default 0 01H ALB 7 ALB R/W R/W Default 0 02H RLB 7 RLB R/W R/W Default 0 03H TAO 7 TAO R/W R/W Default 0 04H LOS 7 LOS R R Default 0 05H ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-17 Primary Register Map (Continued) Address Register R/W Bit 7 Default 10 Hex - TSIA R/W R/W Default 0 11 Hex - TS R/W R/W Default 0 12 Hex R/W R/W Default 0 13 Hex AIS 7 AIS R R Default 0 14 Hex AISM 7 AISM R/W R/W Default 0 15 Hex ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-18 Expanded (Indirect Address Mode) Register Map Address Register R/W Bit 7 Default 00H SING 7 e-SING R/W Default 01H CODE 7 e-CODE R/W Default 02H CRS 7 e-CRS R/W Default 03H RPDN 7 e-RPDN R/W Default 04H TPDN 7 e-TPDN R/W Default 05H ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 3.2 REGISTER DESCRIPTION 3.2.1 PRIMARY REGISTERS ID: Device ID Register (R, Address = 00H) Symbol Position Default An 8-bit word is pre-set into the device as the identification and revision number. This number is different with the functional ID[7:0] ID.7-0 10H changes and is mask programmed. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION DFI: Driver Fault Interrupt Status Register (R, Address = 09H) Symbol Position Default 0 = (Default). Or after a DF read operation. DFI[7:0] DFI.7-0 00H 1 = Any transition on DFn (Corresponding DFMn is set to ‘1’). RS: Software Reset Register (W, Address = 0AH) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION GCF: Global Configuration Register (R/W, Address = 0FH) Symbol Position Default 0 = Normal operation. - GCF Reserved AIS insertion to the system side disabled on LOS. AISE GCF AIS insertion to the system side enabled on LOS Short circuit protection is enabled. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION AIS: Alarm Indication Signal Status Register (R, Address = 13H) Symbol Position Default 0 = Normal operation. (Default) AIS[7:0] AIS.7-0 00H 1 = AIS detected. AISM: Alarm Indication Signal Interrupt Mask Register (R/W, Address = 14H) Symbol Position Default 0 = AIS interrupt is not allowed. (Default) AISM[7:0] AISM ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 3.2.2 EXPANDED REGISTER DESCRIPTION e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00H) Symbol Position Default 0 = Pin TDNn selects single rail mode or dual rail mode. (Default) SING[7:0] SING.7-0 00H 1 = Single rail mode enabled (with CRSn=0) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION e-LBCF: Inband Loopback Configuration Register Symbol Position Default 0 = Normal Operation. (Default) - LBCF.7 Reserved. Loopback Detector Enable LBDE LBCF Inband loopback code detection is disabled. (Default Inband loopback code detection is enabled. Automatic Loopback Enable ALBE LBCF ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION e-LBI: Inband Loopback Interrupt Status Register (R, Expanded Address = 0DH) Symbol Position Default 0 = (Default). Or after a read of e-LBS operation. LBI[7:0] LBI.7-0 00H 1 = Any transition on e-LBSn. (Corresponding e-LBMn and bit LBDE in e-LBCF are both set to 1.) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 4 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2048S supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the TMS and TCK pins ...
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... TDI into the boundary scan register using the Update-DR state. The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2048S logic and the I/O pins is maintained. Primary device 100 Sample/Preload inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 16 PIOS N/A 17 TCLK1 TCLK1 18 TDP1 TDP1 19 TDN1 TDN1 20 RCLK1 RCLK1 21 RDP1 RDP1 22 RDN1 RDN1 23 HZEN1 N/A 24 LOS1 LOS1 25 TCLK0 TCLK0 26 TDP0 TDP0 27 TDN0 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 57 MODE0 MODE0 58 TCLK5 TCLK5 59 TDP5 TDP5 60 TDN5 TDN5 61 RCLK5 RCLK5 62 RDP5 RDP5 63 RDN5 RDN5 64 HZEN5 N/A 65 LOS5 LOS5 66 TCLK4 TCLK4 67 TDP4 TDP4 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION 4.3 TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. 25 shows its state diagram A description of each state follows. Note that the figure contains two main branches to access either the data or ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION Table-22 TAP Controller State Description (Continued) State This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR Exit1-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION ABSOLUTE MAXIMUM RATING Symbol VDDA, VDDD Core Power Supply VDDIO0, VDDIO1 I/O Power Supply VDDT0-7 Transmit Power Supply Input Voltage, any digital pin Vin Input Voltage ESD Voltage, any pin Transient Latch-up Current, any pin ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION POWER CONSUMPTION Symbol E1, 3 Ω Load 50% ones density data: 100% ones density data: E1, 3.3 V, 120 Ω Load 50% ones density data: 100% ones density data: E1, 5 Ω Load 50% ones density data: 100% ones density data: E1, 5.0 V, 120 Ω ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION TRANSMITTER CHARACTERISTICS Symbol V (1) Output Pulse Amplitudes o-p E1, 75 Ω load E1, 120 Ω load T1, 100 Ω load V Zero (space) Level O-S E1, 75 Ω load E1, 120 Ω load T1, 100 Ω load Transmit Amplitude Variation with supply ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION RECEIVER CHARACTERISTICS Symbol ATT Permissible Cable Attenuation (E1: @ 1024 kHz, T1: @ 772 kHz) IA Input Amplitude Differential Interface Single Ended Interface SIR Signal to Interference Ratio Margin SRE Data Decision Threshold (refer to peak input voltage) Data Slicer Threshold ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION JITTER ATTENUATOR CHARACTERISTICS Symbol f Jitter Transfer Function Corner Frequency (–3 dB) -3dB Host mode Hardware mode Jitter Attenuator ( 400 Hz @ 100 kHz ( kHz @ 1.4 kHz @ 70 kHz td Jitter Attenuator Latency Delay ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION TRANSCEIVER TIMING CHARACTERISTICS Symbol MCLK Frequency E1: T1: MCLK Tolerance MCLK Duty Cycle Transmit Path TCLK Frequency E1: T1: TCLK Tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay time of OE low to driver High-Z ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION TCLKn TDn/TDPn BPVIn/TDNn RCLKn RDn/RDPn (CLKE = 1) CVn/RDNn RDn/RDPn (CLKE = 0) CVn/RDNn t1 Figure-26 Transmit System Interface Timing Figure-27 Receive System Interface Timing 52 INDUSTRIAL TEMPERATURE RANGES t2 t8 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION JTAG TIMING CHARACTERISTICS Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to TDO Delay Time TCK TMS TDI TDO Parameter t1 t2 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION PARALLEL HOST INTERFACE TIMING CHARACTERISTICS INTEL MODE READ TIMING CHARACTERISTICS Symbol t1 Active RD Pulse Width t2 Active CS to Active RD Setup Time t3 Inactive RD to Inactive CS Hold Time t4 Valid Address to Inactive ALE Setup Time (in Multiplexed Mode) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION CS RD ALE(=1) A[4:0] D[7:0] RDY INT CS RD ALE AD[7:0] RDY INT t2 t1 t13 ADDRESS t6 t8 t15 Figure-29 Non-Multiplexed Intel Mode Read Timing t2 t1 t11 t12 t13 t16 t4 t6 ADDRESS t8 t15 Figure-30 Multiplexed Intel Mode Read Timing ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION INTEL MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active WR Pulse Width t2 Active CS to Active WR Setup Time t3 Inactive WR to Inactive CS Hold Time t4 Valid Address to Latch Enable Setup Time (in Multiplexed Mode) t5 Invalid WR to Address Hold Time (in Non-Multiplexed Mode) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION MOTOROLA MODE READ TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active DS Setup Time t5 Inactive DS to R/W Hold Time t6 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION MOTOROLA MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active DS Setup Time t5 Inactive DS to R/W Hold Time t6 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION SERIAL HOST INTERFACE TIMING CHARACTERISTICS Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time t5 CS Idle Time t6 SDI to SCLK Setup Time t7 SCLK to SDI Hold Time ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION JITTER TOLERANCE PERFORMANCE E1 JITTER TOLERANCE PERFORMANCE G.823 IDT82V2048S Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TOLERANCE PERFORMANCE AT&T62411 IDT82V2048S Test condition: QRSS; Line code rule B8ZS is used 100 1 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION JITTER TRANSFER PERFORMANCE E1 JITTER TRANSFER PERFORMANCE G.736 IDT82V2048S Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TRANSFER PERFORMANCE AT&T62411 GR-253-CORE TR-TSY-000009 IDT82V2048S Test condition: QRSS; Line code rule B8ZS is used -19 ...
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... IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION ORDERING INFORMATION XXXXXXX IDT Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc Process/ Package Temperature ...