IDT74ALVC16244A Integrated Device Technology, IDT74ALVC16244A Datasheet - Page 5

• Manufacturer Part Number: IDT74ALVC16244A
• Description: 3.3v Cmos 16-bit Buffer/driver With 3-state Outputs
• Manufacturer: Integrated Device Technology

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
L
T
Symbol
Pulse
Generator
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
V
For t
For t
LOAD
V
V
C
HZ
LZ
IH
T
L
OUTPUT 2
OUTPUT 1
(1, 2)
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
Disable High
Disable Low
Enable High
Enable Low
INPUT
Open Drain
V
CC
Test
(1)
V
= 3.3V±0.3V V
IN
300
300
2.7
1.5
50
6
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
T
D.U.T.
= t
V
t
PLH1
CC
PLH2
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
-
t
V
SK
t
OUT
PLH1
(x)
OUT
SK
F
F
or
(
≤ 2ns; t
X
t
V
≤ 2.5ns; t
C
of the Pulse Generator.
PHL1
)
CC
L
t
PHL2
t
PHL2
(2)
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
V
GND
Open
R
Vcc
150
150
t
LOAD
30
500Ω
SK
-
500Ω
ALVC Link
R
≤ 2ns.
t
PHL1
≤ 2.5ns.
(x)
ALVC Link
V
V
0V
V
V
V
V
V
V
IH
T
OH
T
OL
OH
T
OL
Open
V
GND
LOAD
Unit
mV
mV
pF
V
V
V
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
CONTROL
CONTROL
OUTPUT
LOW-HIGH-LOW
OUTPUT
SAME PHASE
TIMING
INPUT
INPUT
INPUT
HIGH
DATA
LOW
OUTPUT
Set-up, Hold, and Release Times
PULSE
PULSE
CLOSED
SWITCH
SWITCH
Enable and Disable Times
ENABLE
OPEN
Propagation Delay
t
t
PZL
PZH
Pulse Width
t
t
PLH
PLH
INDUSTRIAL TEMPERATURE RANGE
V
t
V
V
0V
SU
t
T
SU
LOAD/2
T
t
W
t
t
PHZ
REM
t
DISABLE
H
t
t
PHL
PHL
t
H
t
PLZ
ALVC Link
ALVC Link
ALVC Link
V
V
V
V
0V
V
V
V
V
V
0V
ALVC Link
T
T
V
V
0V
V
V
V
V
V
0V
IH
T
LOAD/2
OL
OL
OH
OH -
IH
T
OH
T
OL
IH
T
+ V
V
V
0V
V
V
0V
V
V
0V
V
V
0V
V
T
T
T
T
IH
IH
IH
IH
HZ
LZ