IDT71V416S Integrated Device Technology, IDT71V416S Datasheet

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IDT71V416S

Manufacturer Part Number
IDT71V416S
Description
3.3v 256k X 16 Static Ram Center Pwr & Gnd Pinout
Manufacturer
Integrated Device Technology
Datasheet

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Features
Functional Block Diagram
©2004 Integrated Device Technology, Inc.
256K x 16 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
– Commercial and Industrial: 10/12/15ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
A0 - A17
BHE
BLE
WE
OE
CS
Address
Buffers
Write
Enable
Buffer
Output
Enable
Buffer
Chip
Select
Buffer
Byte
Enable
Buffers
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
4,194,304-bit
Row / Column
Decoders
Memory
Array
1
Description
as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
16
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
The IDT71V416 has an output enable pin which operates as fast as
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
Drivers
Sense
Amps
Write
and
8
8
8
8
Output
Output
Buffer
Buffer
Buffer
Buffer
Write
Write
High
Byte
High
Byte
Byte
Byte
Low
Low
8
8
8
8
JANUARY 2004
IDT71V416S
IDT71V416L
3624 drw 01
I/O 15
I/O 8
I/O 7
I/O 0
DSC-3624/09

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IDT71V416S Summary of contents

Page 1

... The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Row / Column Decoders Sense 4,194,304-bit 16 Amps Memory and Array Write Drivers 1 IDT71V416S IDT71V416L High 8 8 Byte I/O 15 Output Buffer High 8 8 Byte I/O 8 Write ...

Page 2

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Pin Configurations - SOJ/TSOP SO44 SO44 *Pin 28 can either connected to Vss ...

Page 3

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN, OUT Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 4

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) DC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter |I | Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH DC Electrical Characteristics (V = Min. to Max 0.2V ...

Page 5

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select Low to Output in Low-Z CLZ ...

Page 6

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Read Cycle No. 2 ADDRESS OE CS BHE, BLE DATA OUT NOTES HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t 3. Transition is measured ±200mV from steady state. ...

Page 7

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN NOTES write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. ...

Page 8

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Ordering Information X IDT 71V416 X Die Device Power Revistion Type X XX XXX X Process/ Speed Package Temperature Range 6.42 8 Commercial and Industrial Temperature Ranges Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) Restricted hazardous G substance device ...

Page 9

... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Datasheet Document History 08/5/99 Updated to new format Pg 6 Revised footnote for t 08/31/99 Pg. 1–9 Added Industrial temperature range offering Pg. 9 Added Datasheet Document History 03/24/00 Pg. 6 Changed note to Write cycle No. 1 according to footnotes 08/10/00 Add 48 ball grid array package offering Pg ...

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