IDT71V416S Integrated Device Technology, IDT71V416S Datasheet
IDT71V416S
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IDT71V416S Summary of contents
Page 1
... The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Row / Column Decoders Sense 4,194,304-bit 16 Amps Memory and Array Write Drivers 1 IDT71V416S IDT71V416L High 8 8 Byte I/O 15 Output Buffer High 8 8 Byte I/O 8 Write ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Pin Configurations - SOJ/TSOP SO44 SO44 *Pin 28 can either connected to Vss ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN, OUT Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) DC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter |I | Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH DC Electrical Characteristics (V = Min. to Max 0.2V ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select Low to Output in Low-Z CLZ ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Read Cycle No. 2 ADDRESS OE CS BHE, BLE DATA OUT NOTES HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t 3. Transition is measured ±200mV from steady state. ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN NOTES write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Ordering Information X IDT 71V416 X Die Device Power Revistion Type X XX XXX X Process/ Speed Package Temperature Range 6.42 8 Commercial and Industrial Temperature Ranges Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) Restricted hazardous G substance device ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Datasheet Document History 08/5/99 Updated to new format Pg 6 Revised footnote for t 08/31/99 Pg. 1–9 Added Industrial temperature range offering Pg. 9 Added Datasheet Document History 03/24/00 Pg. 6 Changed note to Write cycle No. 1 according to footnotes 08/10/00 Add 48 ball grid array package offering Pg ...