IDT5V9885T Integrated Device Technology, IDT5V9885T Datasheet - Page 22

• Manufacturer Part Number: IDT5V9885T
• Description: 3.3v Eeprom Programmable Clock Generator
• Manufacturer: Integrated Device Technology

PROGRAMMING THE DEVICE
to be LOW for I
I
byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read.
The frame formats are shown below.
2
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
C PROGRAMMING
I
Hardwired Parameters for the IDT5V9885T
JTAG identification number = 32'b0000_0000001110101100_00000110011_1
Device (slave) address = 7'b1101010
ID Byte for the 5V9885T = 8'b00010000
The 5V9885T is programmed through an I
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.
2
C and JTAG may be used to program the 5V9885T. The I
2
C mode.
SDA
SCL
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a "1" bit.
R/W
0 - Slave will be written by master
1 - Slave will be read by master
Condition
Start
S
2
C-Bus serial interface, and is an I
MSB
1
Figure 2: First Byte Transmittetd on I
1
2
C/JTAG pin selects the I
7-bit slave address
0
Data is stable during
Figure 1: Framing
Data Frame
clock HIGH
1
22
2
0
C slave device. The read and write transfer formats are supported. The first
1
2
C when HIGH and JTAG when LOW. Note that the TRST pin needs
0
2
C Bus
LSB
R/W
ACK from Slave
Condition
Stop
P
INDUSTRIAL TEMPERATURE RANGE
SDA
SCL