MC14526B
Presettable 4−Bit Down
Counters
and N−channel enhancement mode devices in a monolithic structure.
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
MAXIMUM RATINGS
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
The MC14526B binary counter is constructed with MOS P−channel
This device is presettable, cascadable, synchronous down counter
This complementary MOS counter can be used in frequency
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Clock or Negative Transition of Inhibit
Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pb−Free Packages are Available*
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
SS
SS
or V
Rating
v (V
DD
in
). Unused outputs must be left open.
or V
out
) v V
DD
.
Symbol
I
in
V
V
V
T
P
, I
T
T
DD
out
stg
in
in
D
A
L
out
,
and V
−0.5 to V
out
−0.5 to +18.0
−55 to +125
−65 to +150
should be constrained
Value
±10
500
260
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
1
1
A
WL, L
YY, Y
WW, W = Work Week
G
ORDERING INFORMATION
SOIC−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
F SUFFIX
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
Publication Order Number:
1
1
1
MC14526BCP
AWLYYWWG
DIAGRAMS
AWLYWWG
MC14526B
MARKING
ALYWG
14526B
MC14526B/D