SI5013 Silicon Laboratories, SI5013 Datasheet
SI5013
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SI5013 Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5013 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
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... Si5013 2 Rev. 1.4 ...
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... Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Pin Descriptions: Si5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 1.4 Si5013 Page 3 ...
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... Si5013 1. Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Amp Detector DIN– Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 LTR BER_ALM BER Monitor Phase A/D DSP VCO n Lock Detection Rev. 1.4 RATESEL DSQLCH DOUT+ Retime DOUT– CLKOUT+ ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5013 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3.Typical Application Schematic" on page 11. ...
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... Si5013 DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL DATAIN LOS 6 Figure 2. Clock to Data Timing Figure 4. PLL Acquisition Time t LOS Figure 5. LOS Response Rev. 1.4 80% 20% LOS Threshold Level ...
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... Load V OCM Line-to-Line R Single-ended OUT Rev. 1.4 Si5013 Min Typ Max Unit — 180 190 mA — 190 197 — 594 657 mW — 627 682 — 1.50 — V 1.90 2.10 2. — 500 ...
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... Si5013 Table 3. AC Characteristics (Clock and Data 3.3 V ±5 – ° Parameter Symbol Output Clock Rate Output Rise Time—OC-12 Output Fall Time—OC-12 Output Clock Duty Cycle— OC-12/3 Clock to Data Delay OC-12 OC-3 Clock to Data Delay OC-12 OC-3 Input Return Loss 1 Slicing Level Offset ...
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... After falling edge of AQ PWRDN/CAL From the return of valid data T After falling edge of AQ PWRDN/CAL From the return of valid data See "4.4.Operation With- out an External Refer- ence" on page 12. C TOL Rev. 1.4 Si5013 Min Typ Max Unit 60 — — — — — ...
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... Si5013 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Indicator Control Inputs Loss-of-Lock Indicator DIN+ DIN– Si5013 REFCLK+ CLKOUT+ REFCLK– CLKOUT– 100 VDD 10 kΩ 0.1 µF Data Slice Level Set Bit Error Rate Level Set Rev. 1.4 Si5013 Indicator DOUT+ Recovered Data DOUT– Recovered Clock 11 ...
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... DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5013 uses the reference clock to center the VCO output frequency so that clock and data is recovered from the input data stream ...
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... When it is anticipated that very low-level DIN signals will be encountered, the introduction of an adequate amount of LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of LOS signal hysteresis for the Si5013 CDR. The value of Rev. 1.4 Si5013 40 mV/V 1.875 V 2 ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. 14 4.11.1. Jitter Tolerance The Si5013’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
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... Device Grounding The Si5013 uses the GND pad on the bottom of the 28- pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground ...
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... Ω RFCLK– 10 kΩ GND Si5013 2.5 V (±5 Ω DIN+ 50 Ω 5 kΩ 50 Ω 7.5 kΩ Ω DIN– GND Si5013 2.5 V (±5%) 2.5 kΩ Ω RFCLK + 10 kΩ 2.5 kΩ 50 Ω RFCLK – 10 kΩ 0.1 µF GND Rev. 1.4 ...
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... Figure 13. Single-Ended Input Termination for DIN (ac coupled) 4.19. Differential Output Circuitry The Si5013 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7 ...
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... DOUT– TDI LOL Figure 15. Si5013 Pin Configuration Table 8. Si5013 Pin Descriptions I/O Signal Level I LVTTL Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. ...
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... Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 7 LOL 8 LTR 9 LOS 10 DSQLCH 11,14,18,21, VDD 25 12 DIN+ 13 DIN– 15 GND 16 DOUT– 17 DOUT+ 19 RESET/CAL I/O Signal Level O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9 ...
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... Si5013 Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 20 REXT 22 CLKOUT– 23 CLKOUT+ 24 CLKDSBL 26 BER_LVL 27 BER_ALM 28 NC GND Pad, 2 GND 20 I/O Signal Level External Bias Resistor. This resistor is used to establish internal bias cur- rents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. ...
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... Ordering Guide Part Number Package Si5013-X-GM 28-lead MLP Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. Voltage Lead-Free Temperature 3.3 Yes Rev. 1.4 Si5013 – °C 21 ...
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... Si5013 7. Package Outline Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 16. 28-Lead Micro Leaded Package (MLP θ SEATING ...
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... Updated reference clocks tolerance. " ! "3.Typical Application Schematic" on page 11. Added 1% to Rext. " ! "4.11.PLL Performance" on page 14. Removed OC-24 note. " ! Table 8 on page 18. Added no-hysteresis text to BER_LVL. " ! Updated "6.Ordering Guide" on page 21. Added “X” to part number. " Rev. 1.4 Si5013 23 ...
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... Si5013 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...