MCP3302-I/ST Microchip Technology, MCP3302-I/ST Datasheet - Page 22

• Manufacturer Part Number: MCP3302-I/ST
• Description: 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface
• Manufacturer: Microchip Technology

MCP3302/04
7.3
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the ris-
ing edge. Because communication with the MCP3302/
04 devices may not need multiples of eight clocks, it will
be necessary to provide more clocks than are required.
This is usually done by sending ‘leading zeros’ before
the start bit. As an example, Figure 7-4 and Figure 7-5
shows how the MCP3302/04 devices can be interfaced
to a MCU with a hardware SPI port. Figure 7-4 depicts
the operation shown in SPI Mode 0,0 which requires
that the SCLK from the MCU idles in the ‘low’ state,
while Figure 7-5 shows the similar case of SPI Mode
1,1 where the clock idles in the ‘high’ state.
As shown in Figure 7-4, the first byte transmitted to the
A/D Converter contains 6 leading zeros before the start
FIGURE 7-4:
FIGURE 7-5:
DS21697A-page 22
X = Don’t Care Bits
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X = Don’t Care Bits
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
SCLK
D
OUT
D
CS
SCLK
D
IN
OUT
D
CS
Using the MCP3302/04 with
Microcontroller (MCU) SPI Ports
IN
MCU latches data from A/D Converter
on rising edges of SCLK
SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK idles high).
MCU latches data from A/D Converter
on rising edges of SCLK
1
0
?
Data stored into MCU receive register
after transmission of first 8 bits
1
?
0
Data stored into MCU receive register
after transmission of first 8 bits
2
0
?
2
?
0
3
0
?
3
?
0
HI-Z
4
0
?
HI-Z
4
Start
?
0
Start
5
Data is clocked out of
A/D Converter on falling edges
1
?
Start
5
SGL/
DIFF
Bit
?
1
Data is clocked out of
A/D Converter on falling edges
Start
SGL/
DIFF
6
SGL/
DIFF
Bit
?
6
SGL/
DIFF
?
D2
7
D2
D2
?
7
D2
?
D1
8
D1
?
D1
D1
?
8
D0
DO
9
D0
?
Data stored into MCU receive register
after transmission of second 8 bits
DO
9
?
Data stored into MCU receive register
after transmission of second 8 bits
10
X
?
NULL
10
BIT
X
?
NULL
(Null)
11
BIT
X
0
11
(Null)
SB
X
0
12
SB
SB
12
X
bit. Arranging the leading zeros this way produces the
13 data bits to fall in positions easily manipulated by the
MCU. The sign bit is clocked out of the A/D Converter
on the falling edge of clock number 11, followed by the
remaining data bits (MSB first). After the second eight
clocks have been sent to the device, the MCU receive
buffer will contain 2 unknown bits (the output is at high
impedance for the first two clocks), the null bit, the sign
bit and the 4 highest order bits of the conversion. After
the third byte has been sent to the device, the receive
register will contain the lowest order eight bits of the
conversion results. Easier manipulation of the con-
verted data can be obtained by using this method.
Figure 7-5 shows the same situation in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
SB
B11 B10 B9
X
13
B11 B10 B9
B11 B10 B9
13
X
B11 B10 B9
X
14
14
X
X
15
15
X
X
B8
16
B8
X
B8
X
B8
16
B7
17
Don’t Care
B7
Don’t Care
X
B7
Don’t Care
17
Data stored into MCU receive register
after transmission of last 8 bits
B7
X
B6
Data stored into MCU receive register
after transmission of last 8 bits
18
B6
X
B6 B5
18
B6
X
B5
2001 Microchip Technology Inc.
19
B5
X
19
B5
X
B4
20
B4
B4
X
20
B4
X
B3 B2
21
B3
X
21
B3
B3
X
22
B2
22
B2
X
B2
X
B1
23
B1
23
X
B1 B0
B1
X
B0
24
B0
X
24
B0
X