MCP3550 Microchip Technology, MCP3550 Datasheet - Page 21

• Manufacturer Part Number: MCP3550
• Description: Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
• Manufacturer: Microchip Technology

5.5
It is required that the microcontroller SPI port be config-
ured to clock out data on the falling edge of clock and
latch data in on the rising edge. Figure 5-6 depicts the
operation shown in SPI mode 1,1, which requires that
the SCK from the MCU idles in the High state, while
Figure 5-7 shows the similar case of SPI Mode 0,0,
where the clock idles in the Low state. The waveforms
in the figures are examples of an MCU operating the
SPI port in 8-bit mode, and the MCP3550/1/3 devices
do not require data in 8-bit groups.
FIGURE 5-6:
FIGURE 5-7:
© 2007 Microchip Technology Inc.
SDO/RDY
Receive
Buffer
MCU
SCK
CS
Using The MCP3550/1/3 with
Microcontroller (MCU) SPI Ports
Data stored into MCU receive
register after transmission of
first byte
DR
SDO/RDY
Receive
DR
Buffer
OH OL 21 20 19 18 17
MCU
SCK
O O
H L
CS
21 20 19 18 17
Data stored into MCU receive
register after transmission of
first byte
OL OH 21 20 19 18 17 16
SPI Communication – Mode 1,1.
SPI Communication – Mode 0,0.
D
R
O O
H L
21 20 19 18 17
16
Data stored into MCU receive
register after transmission of
second byte
16
15 14 13 12 11 10 9
15
16
14 13 12 11 10 9
Data stored into MCU receive
register after transmission of
second byte
15 14 13 12 11 10 9
15 14 13 12 11 10 9
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY line prior to a falling edge of
the clock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
8
Data stored into MCU receive
register after transmission of
third byte
8
7
8
7
6
8
6 5 4 3 2
5
Data stored into MCU receive
register after transmission of
third byte
7
4
7 6 5 4 3 2 1
6
3 2
5
1
4
1
MCP3550/1/3
3 2
0
Data stored into MCU receive
register after transmission of
fourth byte
0
1
0
0
DS21950D-page 21