TDA8034T Philips Semiconductors, TDA8034T Datasheet - Page 7

• Manufacturer Part Number: TDA8034T
• Description: Smart Card Interface
• Manufacturer: Philips Semiconductors

NXP Semiconductors
TDA8034T_TDA8034AT_1
Product data sheet
8.4 Input and output circuits
The clock frequency is selected using pin CLKDIV1 to be either
TDA8034T or f
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either
or f
45 % and 55 %.
Table 4.
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
V
referenced to V
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay t
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (t
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the
TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of
0.9V
dependent on the internal pull-up resistor value and load current. The current sent to and
received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
Pin CLKDIV1 level
HIGH
LOW
Fig 5.
CC
xtal
and/or between pins I/OUC and V
CC
or
, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is
1
enclkin and clkxtal are internal signal names.
Basic layout for using an external clock
2
Clock configuration
f
xtal
xtal
CC
on TDA8034AT, the frequency dividers guarantee a duty cycle between
or
xtal
and pin I/OUC to V
1
on pin CLK should be between 45 % and 55 %. If an external clock
2
Rev. 01 — 5 February 2010
f
xtal
Pin CLK level
TDA8034T
1
1
2
4
on TDA8034AT as shown in
f
f
xtal
xtal
enclkin
DD(INTF)
DIGITAL
DD(INTF)
TDA8034T; TDA8034AT
XTAL1
MULTIPLEXER
, thus allowing operation at V
clkxtal
CRYSTAL
, both lines enter the idle state. Pin I/O is
XTAL2
001aak992
Table
TDA8034AT
1
f
xtal
2
1
f
2
xtal
f
4.
xtal
w(pu)
1
2
or
www.DataSheet4U.com
f
). After this sequence,
xtal
Smart card interface
1
4
or
© NXP B.V. 2010. All rights reserved.
f
xtal
1
CC
4
on TDA8034T
f
xtal
V
on
DD(INTF)
7 of 29
d
.
,