74F569SC Fairchild Semiconductor, 74F569SC Datasheet

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74F569SC

Manufacturer Part Number
74F569SC
Description
IC COUNTER BINARY 4BIT 20-SOIC
Manufacturer
Fairchild Semiconductor
Series
74Fr
Datasheet

Specifications of 74F569SC

Logic Type
Binary Counter
Direction
Up, Down
Number Of Elements
1
Number Of Bits Per Element
4
Reset
Asynchronous/Synchronous
Count Rate
90MHz
Trigger Type
Positive Edge
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing
-
© 2000 Fairchild Semiconductor Corporation
74F569SC
74F569SJ
74F569PC
74F569
4-Bit Bidirectional Counter with 3-STATE Outputs
General Description
The 74F569 is a fully synchronous, reversible counter with
3-STATE outputs. The 74F569 is a binary counter, featur-
ing preset capability for programmable operation, carry loo-
kahead for easy cascading, and a U/D input to control the
direction of counting. For maximum flexibility there are both
synchronous and master asynchronous reset inputs as well
as both Clocked Carry (CC) and Terminal Count (TC) out-
puts. All state changes except Master Reset are initiated by
the rising edge of the clock. A HIGH signal on the Output
Enable (OE) input forces the output buffers into the high
impedance state but does not prevent counting, resetting
or parallel loading.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
FAST
Order Number
is a registered trademark of Fairchild Semiconductor Corporation.
Package Number
IEEE/IEC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009565
Features
Connection Diagram
Synchronous counting and loading
Lookahead carry capability for easy cascading
Preset capability for programmable operation
3-STATE outputs for bus organized systems
Package Description
April 1988
Revised October 2000
www.fairchildsemi.com

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74F569SC Summary of contents

Page 1

... Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. Ordering Code: Order Number Package Number 74F569SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F569SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ...

Page 2

Unit Loading/Fan Out Pin Names P –P Parallel Data Inputs 0 3 CEP Count Enable Parallel Input (Active LOW) CET Count Enable Trickle Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) PE Parallel Enable Input (Active LOW) U/D ...

Page 3

CC Truth Table Inputs SR PE CEP CET TC CP (Note ...

Page 4

Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 ...

Page 5

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 6

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH (PE HIGH or LOW) PHL n t Propagation Delay PLH PHL t Propagation Delay PLH t CET to ...

Page 7

AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or LOW (H) Hold Time, HIGH or LOW (H) Setup Time, HIGH ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide www.fairchildsemi.com Package Number M20B 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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