TDA8961 Philips Semiconductors, TDA8961 Datasheet
TDA8961
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TDA8961 Summary of contents
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... DATA SHEET TDA8961 ATSC Digital Terrestrial TV demodulator/decoder Objective specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 2000 May 19 ...
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... Division Multiplexing (OFDM) channel decoder. APPLICATIONS Digital ATSC compliant TV receiver Personal computers with digital television capabilities Set top-boxes. PACKAGE DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body14 20 2 Objective specification 2 1 (Rate Ungerboeck code based C-bus is possible (default). TDA8961 2 C. VERSION SOT318-2 ...
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... SAW FILTER Fig.1 Front-end design for a hybrid TV system using the TDA8980 and TDA8961. 2000 May 19 Down converts the incoming 6 MHz wide 8-VSB IF signal to a low-IF signal centered at 4 MHz: The low-IF signal is then digitized, using an on-chip 10-bit A/D converter, and fed to the TDA8961 for further processing ...
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... SAW RF FILTER TUNER RF Fig.2 Front-end design for the TDA8961 using a stand-alone IF down converter (TDA9829) and A/D converter. 2000 May 19 correct bytes. The decoded stream is then de-randomized using a pseudo-random binary sequence (PRBS) and the data passed to a FIFO which prevents the appearance of irregular gaps in the output data ...
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... Nyquist filter roll-off factor ro t acquisition time acq T ambient temperature amb P total power dissipation tot Note 1. Corresponds to 12 training sequences. 2000 May 19 CONDITIONS MIN note Objective specification TDA8961 TYP. MAX. UNIT 3.3 3.6 V 390 mA 12 MHz 10.76 Msymbols/s 36 MHz 4 MHz dB 11.5 % 290 ms + ...
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... TRELLIS DECODER 2 I C-BUS INTERFACE DE-INTERLEAVER REED SOLOMON DECODER CLOCK GENERATION DE-RANDOMIZER OUTPUT FORMATTER TDA8961 FSHNDSHK PDOSYNC PDO7 TO PDO0 PDOVAL SSYNC Fig.3 Block diagram. 6 Objective specification TDA8961 ADCLK 80 66 AGCOUT 43, 44, 45, 47, 48, 49, 51 MGU087 PDOCLK PDOERR ...
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... O transport stream interface packet error signal (3-state) I/O supply voltage 1 (3 transport stream interface packet sync indicator signal (3-state) O transport stream interface packet data valid indicator signal (3-state) 7 Objective specification TDA8961 DESCRIPTION ...
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... V) I external crystal O external crystal analog ground 1 analog supply 2 (3.3 V) not connected I/O supply 5 (3 MHz clock signal I/O ground 5 I asynchronous reset (active LOW) O front-end lock indicator O equalizer lock indicator I incoming data sampling clock signal (36 MHz) 8 Objective specification TDA8961 DESCRIPTION ...
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... TDO is a 3-state output in accordance with IEEE 1149.1. 2. Pin TRST is active LOW. It can be used to immediately force the Test Access Port (TAP) controller to the test logic reset state (normal operation) in accordance with IEEE 1149.1. 2000 May 19 9 Objective specification TDA8961 ...
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... V SSD1 SCL 15 SDA 16 V DDD2 17 V SSD2 18 TDI 19 TMS 20 TCK 21 TRST 22 TDO 23 V DDD3 24 2000 May 19 TDA8961 Fig.4 Pin configuration. 10 Objective specification TDA8961 64 V SSQ4 63 n.c. 62 n. DDQ4 59 n.c. 58 n. SSQ3 55 n. DDQ3 52 PDO0 51 PDO1 50 V SSQ2 ...
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... The 10-bit wide data from either the TDA8980 or a stand-alone A/D converter (TDA8763A is recommended) arrives at the sample rate converter input of the TDA8961 via inputs ADIN9 to ADIN0. The format of the incoming samples can be programmed by the status of I bit AD_FMT (see Table 9). The format can be either two’s complement or binary ...
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... If segment sync lock is lost, either pin LOCKINDIC goes 2 C-bus LOW hardware reset is applied to the TDA8961 and the finite state machine returns to state 0. State 2: equalizer training The finite state machine remains in state 1 until the MSE of the equalized training sequence falls between two specific threshold values ...
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... FIFO, the number of parity bytes transferred can vary slightly. The PDOCLK signal runs continuously and is not affected by a reset. In parallel output format, it has a frequency of 3 MHz. When the TDA8961 is trying to acquire a channel, the PDOERR signal goes HIGH (I occurs, the PDOVAL signal stays LOW. S ...
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... Sync byte. (2) The polarity of these signals is programmable. 2000 May 19 (2) 2 186 187 (3) (3) Fig.5 Parallel output format. LSB byte 1 byte 187 Fig.6 Serial output format. 14 Objective specification TDA8961 (2) (2) (2) ( MGU090 0 MGU091 ...
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... Figure 7 shows the structure of the so-called transport stream packet header of which only the first two bytes are significant to the TDA8961. The first byte in each header is the sync byte which must have the same value for all packets in accordance with the MPEG-2 standard specification ...
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... Support for only 7-bit addressing and the ability to externally modify the slave address. A typical system using the I Fig.8. The TDA8961 is acting as a slave and is connected to a master via the I be noted that the SCL and SDA lines are connected to separate pull-up resistors. ...
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... I with the correct protocols, and with bit R/W set to either 1 (write data (read data). The slave address of the TDA8961 is given in Table 6. Bits are preset, but bits A1 and A0 can be set via their corresponding external pins. ...
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... DATA A ( acknowledge (SDA LOW) ( not acknowledge (SDA HIGH) ( STOP condition (8) Data transferred (n bytes + acknowledge). (1) (1)(3) (4)(5) (4) (1)(5) R/W A DATA A ( not acknowledge (SDA HIGH). ( STOP condition. (8) Data transferred (n bytes + acknowledge). 18 Objective specification TDA8961 (1) (4)(5)(6) (1)(7) DATA A/A P (8) MGR607 (4) (1)(6) (1)(7) DATA A P (8) MGR608 ...
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Acrobat reader. white to force landscape pages to be ... 2 I C-BUS REGISTER MAP 2 Table 7 I C-bus write register overview ADDRESS ...
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Acrobat reader. white to force landscape pages to be ... ADDRESS FUNCTION D7 D6 (HEX ...
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... CR_RESET 0 1 Notes 1. Operating modes and control parameters of all sections in the TDA8961 are not affected. 2. Operating modes and control parameters of all sections in the TDA8961 are reset to their initial values. Table 9 Sample rate converter settings (write) BIT NAME BIT VALUE AD_FMT 0 1 ...
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... SER is calculated over a 1 second period (default) SER is calculated over a 4 second period SER is calculated over a 8 second period SER is calculated over a 16 second period SER threshold value (used if SER_RST is set to 1) normal operation (default) TDA8961 is reset when the SER exceeds 2.5 22 Objective specification TDA8961 ...
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... Note 1. This register allows the type and version of the TDA8961 to be read by the controlling host. The TYPE field contains 1H corresponding to the TDA8961. The VERSION field contains EH corresponding to the TDA8961 version N1E. Philips Semiconductors reserves the right to change the values in this register for future versions of the TDA8961 ...
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... Philips Semiconductors ATSC Digital Terrestrial TV demodulator/decoder Table 19 Transport stream interface (read) BIT NAME BIT VALUE SER Table 20 TDA8961 version (read) BIT NAME BIT VALUE TYPE 0001 VERSION 1110 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134) SYMBOL PARAMETER ...
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... All supply connections must be made to the same external power supply unit. 2. Open drain output, determined by V 2000 May 19 CONDITIONS 2.7 2.0 0.85V 0.5 0.7V 0 note 0 via an external pull-up resistor Objective specification TDA8961 MIN. TYP. MAX. 3.3 3.6 390 0. 0. + UNIT ...
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... Objective specification TDA8961 TYP. MAX. UNIT MHz % ...
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... This is calculated by multiplying 188 bytes (the length of a packet) by the PDOCLK clock cycle period, multiplied total capacitance of one bus line in pF. b 2000 May 19 CONDITIONS MIN. 0 1.3 0.6 1.3 0.6 0.6 0.6 0 100 tbf note 0. 0. Objective specification TDA8961 TYP. MAX. UNIT 400 kHz 0 tbf ns 300 ns 300 ns 400 ...
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... ADIN9 to ADIN0 T cy(PDOCLK)(par) handbook, full pagewidth PDOCLK t PDOCLKL(par) PDOSYNC | t d(o)(par) PDOVAL PDOERR PDO7 to 47H PDO0 Fig.12 Transport stream interface timing (parallel output format). 2000 May 19 T cy(ADCLK) t su(A/D) Fig.11 A/D interface timing. t PDOCLKH(par PDOVALH(par) 28 Objective specification TDA8961 t h(A/D) valid MGU092 t PDOVALL(par) MGU093 ...
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... PDOVAL PDOERR PDO0 0 1 Fig.13 Transport stream interface timing (serial output format). handbook, full pagewidth TCK TDO 2000 May 19 t PDOSYNCH(ser PDOVALH(ser d(TCK-TDO) t su(i)(TCK) Fig.14 JTAG I/O timing. 29 Objective specification t PDOVALL(ser) t h(i)(TCK) valid MGU095 TDA8961 MGU094 ...
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Acrobat reader. white to force landscape pages to be ... SDA t BUF t LOW t r SCL t HD;STA t HD;DAT P S ...
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... 0.45 0.25 20.1 14.1 24.2 0.8 0.30 0.14 19.9 13.9 23.6 REFERENCES JEDEC EIAJ MO-112 18.2 1.0 1.95 0.2 0.2 0.1 17.6 0.6 EUROPEAN PROJECTION Objective specification TDA8961 SOT318 detail X (1) ( 1.0 1 0.6 0.8 0 ISSUE DATE 97-08-01 99-12-27 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 32 Objective specification TDA8961 ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 May 19 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 33 Objective specification TDA8961 (1) REFLOW suitable suitable suitable suitable suitable ...
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... C components conveys a license under the Philips’ system provided the system conforms to the I 34 Objective specification TDA8961 (1) These products are not Philips Semiconductors 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors ATSC Digital Terrestrial TV demodulator/decoder 2000 May 19 NOTES 35 Objective specification TDA8961 ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...