MCP6283-E/SL Microchip Technology, MCP6283-E/SL Datasheet - Page 11

• Manufacturer Part Number: MCP6283-E/SL
• Description: 450 uA, 5 MHz Rail-to-Rail Op Amp
• Manufacturer: Microchip Technology

3.4
The MCP6285 is a dual op amp with chip select (CS).
The chip select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This feature is provided by connecting the output of op
amp A to the non-inverting input of op amp B, as shown
in Figure 3-4. The chip select input, which can be
connected to a microcontroller I/O line, puts the device
in Low Power mode. Refer to Section 3.3 “MCP6283/5
Chip Select (CS)”.
FIGURE 3-4:
The key issue to note from this configuration is that the
output of op amp A is loaded by the input impedance.
The input impedance of the op amp is typically
10
(Refer to Section 3.5 “Capacitive Loads” for further
details regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as V
V
is limited to V
10 k load), the non-inverting input range of op amp B
is limited to the common mode input range of
V
 2004 Microchip Technology Inc.
V
V
DD
SS
13
INA
INA
+ 20 mV and V
+ 300 mV. However, since the output of op amp A
+
–
|| 6 pF, as specified in the DC specification table
Cascaded Dual Op Amps
(MCP6285)
2
3
OL
A
V
and V
OUTA
DD
1
MCP6285
/V
Cascaded Gain Amplifier.
– 20 mV.
OH
INB
CS
(20 mV from the rails with a
+
5
V
INB
6
–
SS
B
– 300 mV and
7
V
OUTB
3.5
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The band-
width will generally be lower than the bandwidth with no
capacitive load.
FIGURE 3-5:
stabilizes large capacitive loads.
Figure 3-6 gives recommended R
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (C
circuit's noise gain. For non-inverting gains, G
Signal Gain are equal. For inverting gains, G
1+|Signal Gain| (e.g., -1 V/V gives G
FIGURE 3-6:
for Capacitive Loads.
After selecting R
resulting frequency response peaking and step
response overshoot. Modify R
response is reasonable. Bench evaluation and simula-
tions with the MCP6281/2/3/4/5 SPICE macro model
are very helpful.
V
IN
1,000
100
10
Capacitive Loads
10
MCP6281/2/3/4/5
Normalized Load Capacitance; C
MCP6281
+
–
ISO
for your circuit, double-check the
100
Output Resistor, R
Recommended R
ISO
in Figure 3-5) improves the
G
G
G
R
N
N
N
L
ISO
ISO
/G
= 1 V/V
= 2 V/V
ISO
4 V/V
1,000
C
N
's value until the
), where G
N
DS21811C-page 11
L
values for differ-
= +2 V/V).
L
/G
ISO
ISO
N
(pF)
N
V
values
N
and the
10,000
OUT
is the
N
is