74ABT657D Philips Semiconductors, 74ABT657D Datasheet - Page 2

• Manufacturer Part Number: 74ABT657D
• Description: Octal transceiver with parity generator/checker 3-State
• Manufacturer: Philips Semiconductors

FEATURES
DESCRIPTION
The 74ABT657 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers
with 3-State outputs and an 8-bit parity generator/checker, and is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 64mA. The
Transmit/Receive (T/R) input determines the direction of the data
flow through the bidirectional transceivers. Transmit (active-High)
enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
Philips Semiconductors
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
1995 Dec 11
Combinational functions in one package
Low static and dynamic power dissipation with high speed and
high output drive
Output capability: +64mA/–32mA
Power-up 3-State
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Octal transceiver with parity generator/checker
(3-State)
SYMBOL
I
t
t
C
C
PLH
PHL
CCZ
I/O
IN
PACKAGES
ODD/EVEN
ERROR
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
V
T/R
CC
A0
A1
A2
A3
A4
A5
A6
A7
12
10
11
1
2
3
4
5
6
7
8
9
TOP VIEW
PARAMETER
TEMPERATURE RANGE
24
23
22
20
19
18
17
16
15
14
13
21
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
OE
B0
B1
B2
B3
GND
GND
B4
B5
B6
B7
PARITY
C
V
Outputs disabled;
V
Outputs disabled; V
SA00181
L
I
O
= 0V or V
= 50pF; V
= 0V or V
OUTSIDE NORTH AMERICA
2
CC
T
CC
CC
amb
The Output Enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
High. The parity select (ODD/EVEN) input gives the user the option
of odd or even parity systems. The parity (PARITY) pin is an output
from the generator/checker when transmitting from the port A to B
(T/R = High) and an input when receiving from port B to A port (T/R
= Low). When transmitting (T/R = High) the parity select
(ODD/EVEN) input is set, then the A port data is polled to determine
the number of High bits. The parity (PARITY) output then goes to the
logic state determined by the parity select (ODD/EVEN) setting and
by the number of High bits on port A. For example, if the parity
select (ODD/EVEN) is set Low (even parity), and the number of
High bits on port A is odd, then the parity (PARITY) output will be
High, transmitting even parity. If the number of High bits on port A is
even, then the parity (PARITY) output will be Low, keeping even
parity. When in receive mode (T/R = Low) the B port is polled to
determine the number of High bits. If parity select (ODD/EVEN) is
Low (even parity) and the number of Highs on port B is:
(1) odd and the parity (PARITY) input is High, then ERROR will be
(2) even and the parity (PARITY) input is High, then ERROR will be
PIN DESCRIPTION
74ABT657 PW
= 5V
74ABT657 DB
74ABT657 N
74ABT657 D
23, 22, 21, 20,
17, 16, 15, 14
CONDITIONS
= 25 C; GND = 0V
SYMBOL
2, 3, 4, 5,
6, 8, 9, 10
CC
High, signifying no error.
asserted Low, indicating an error.
18, 19
=5.5V
13
12
24
11
1
7
PIN NUMBER
ODD/EVEN
PARITY
ERROR
A0 - A7
B0 - B7
GND
V
T/R
OE
CC
NORTH AMERICA
74ABT657PW DH
74ABT657 DB
74ABT657 N
74ABT657 D
Parity output
Parity select input
Error output
Transmit/receive input
A port 3-State outputs
B port 3-State outputs
Output enable input (active-Low)
Ground (0V)
Positive supply voltage
NAME AND FUNCTION
TYPICAL
500
3.3
4
7
Product specification
74ABT657
DWG NUMBER
853–1615 16106
SOT222-1
SOT137-1
SOT340-1
SOT355-1
UNIT
pF
pF
nA
ns