HT45R36 Holtek Semiconductor, HT45R36 Datasheet
HT45R36
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HT45R36 Summary of contents
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... RAM General Description The HT45R36 is an 8-bit high performance, RISC archi- tecture microcontroller device specifically designed for cost-effective multiple I/O control product applications. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, Power Down and Rev ...
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... Block Diagram Pin Assignment Rev. 1.00 2 September 28, 2006 HT45R36 ...
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... In the case of the RC oscillator, OSC2 can be used to monitor the system clock. Its frequency is 1/4 system clock. 0. +6.0V Storage Temperature ............................ 125 0. +0.3V Operating Temperature........................... HT45R36 Description Total............................................................ 200mA September 28, 2006 ...
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... No load, f SYS 3V No load, system HALT load, system HALT 5V LVR enabled 3V V =0. =0. =0. =0. HT45R36 Ta=25 C Min. Typ. Max. Unit 2.2 5.5 V 3.3 5 =4MHz =8MHz 0. 0.7V ...
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... Interrupt Pulse Width INT t Low Voltage Reset Time LVR Rev. 1.00 Test Conditions Parameter V Conditions DD 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5. Without WDT prescaler 5V Without WDT prescaler Wake-up from HALT 5 HT45R36 Ta=25 C Min. Typ. Max. Unit 400 4000 kHz 400 8000 kHz 0 4000 kHz 0 8000 kHz 45 90 180 s 32 ...
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... Program Counter S10 Program Counter S10~S0: Stack register bits @7~@0: PCL bits 6 HT45R36 * ...
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... Table Location P10~P8: Current program counter bits 7 HT45R36 Location 010H This location is reserved for the external RC oscilla- tion converter interrupt service program external RC oscillation converter interrupt results from an ex- ternal RC oscillation converter interrupt is activated, and the interrupt is enabled and the stack is not full, the program begins execution at this location ...
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... Bit 7 of the memory pointers are not implemented. How- ever, it must be noted that when the memory pointers in this device is read, a value of 1 will be read. 8 September 28, 2006 HT45R36 ...
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... PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 9 HT45R36 or CLR WDT instruction or a system September 28, 2006 ...
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... If only one stack is left and enabling the interrupt is not well controlled, the original control sequence may be dam- aged once the CALL is executed in the interrupt sub- routine. 10 September 28, 2006 HT45R36 1 04H 2 08H 3 0CH 4 ...
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... Writing data to the WS2, WS1, WS0 bits in the WDTS register, can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio will be 1:128, and the maximum time-out period will be 2.1s at 5V. If the internal WDT os- 11 HT45R36 September 28, 2006 ...
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... Once a wake-up event occurs, it takes 1024 t mal operation. In other words, a dummy period will be in- serted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subrou- Watchdog Timer 12 HT45R36 (system clock periods) to resume nor- SYS September 28, 2006 ...
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... Program Counter Interrupt Prescaler WDT Timer/Event Counter Off Input/Output Ports Stack Pointer RESET Conditions Note: 13 HT45R36 000H Disable Clear Clear. After master reset, WDT begins counting Input mode Points to the top of the stack Reset Circuit * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference ...
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... HT45R36 RES Reset WDT Time-out (HALT) (HALT)* -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ---- ---0 ---- ---0 ---- ---0 uuuu uuuu uuuu uuuu ...
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... To enable or disable timer counting (0=disabled; 1=enabled) Unused bit, read define the operating mode, TM1, TM0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register 15 HT45R36 September 28, 2006 ...
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... Timer A overflow or Timer B overflow. (0= Timer A overflow; 1= Timer B overflow) Define RC oscillation converter mode. (0= Disable RC oscillation converter mode; 1= Enable RC oscillation converter mode) Unused bit, read as 0 4-bit read/write registers for user defined. RCOCR (25H) Register External RC Oscillation Converter 16 HT45R36 September 28, 2006 ...
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... Clear External RC Oscillation Converter interrupt request flag ; Give timer A initial value ; Timer A count 1000 time and then overflow ; Give timer B initial value ; Timer A clock source=f /4 and timer on SYS ; Polling External RC Oscillation Converter interrupt request flag ; Clear External RC Oscillation Converter interrupt request flag ; Program continue 17 HT45R36 September 28, 2006 ...
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... Analog switch 14 on, other analog switch off 01110b= Analog switch 15 on, other analog switch off 01111b= Analog switch 16 on, other analog switch off 1xxxxb= All analog switch off and RC OSC always off. Unused bit, read as 0 ASCR (1AH) Register Analog Switch 18 HT45R36 September 28, 2006 ...
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... The PA0, PA1 and PA2 are pin-shared with INT0, INT1 and TMR pins, respectively recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Input/Output Ports 19 HT45R36 September 28, 2006 ...
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... WDTOSC or f Enable or disable instruction Disable or enable X tal mode or RC mode Disable, rising edge, falling edge or double edge Disable, rising edge, falling edge or double edge 20 HT45R36 and V is shown below. DD LVR V is the voltage range for proper chip opera- OPR tion at 4MHz system clock ...
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... Application Circuits Application Circuit Application Circuit 1 Rev. 1.00 21 September 28, 2006 HT45R36 ...
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... C 1~C sensor sensor Rev. 1.00 C1, C2 10pF 10pF 10pF 10pF 10pF 25pF 25pF 35pF 68pF 300pF 300pF 300pF 300pF 16 are the resistance sensors. 16 are the capacitance sensors. 22 HT45R36 R1 12k 4.3k 10k 4.7k 12k 10k 15k 15k 15k 12k 12k 12k 12k September 28, 2006 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Description 23 HT45R36 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 24 HT45R36 Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x TO PDF OV Z Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] TO PDF HT45R36 September 28, 2006 ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO PDF OV Z Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO PDF HT45R36 September 28, 2006 ...
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... PDF and PDF Complement data memory Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO PDF HT45R36 September 28, 2006 ...
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... PDF OV Z Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. ACC [ PDF HT45R36 September 28, 2006 ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr TO PDF OV Z Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] TO PDF HT45R36 September 28, 2006 ...
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... PDF OV Z Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TO PDF HT45R36 September 28, 2006 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO PDF HT45R36 September 28, 2006 ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 TO PDF HT45R36 September 28, 2006 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m] 1)=0, ACC ([ PDF HT45R36 ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Skip if [m]. PDF HT45R36 ...
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... Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO PDF HT45R36 September 28, 2006 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Note that this instruction is not valid for HT48R07A-1/HT48C07 [m] ROM code (low byte) TBLH ROM code (high byte) TO PDF HT45R36 September 28, 2006 ...
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... ACC XOR [m] TO PDF OV Z Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x TO PDF HT45R36 September 28, 2006 ...
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... Package Information 44-pin QFP (10´10) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT45R36 Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 September 28, 2006 ...
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... QFP (14´14) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT45R36 Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 September 28, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or sys- tems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 40 September 28, 2006 HT45R36 ...