USB2504-JD Standard Microsystems Corp., USB2504-JD Datasheet - Page 27

• Manufacturer Part Number: USB2504-JD
• Description: Interface, Integrated USB2.0 Compatible 4-Port Hub
• Manufacturer: Standard Microsystems Corp.

Integrated USB2.0 Compatible 4-Port Hub
Datasheet
SMSC USB2504
5.3.6
5.3.7
5.3.8
5.3.9
ADDR
REG
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
in the “Timing Diagram” section.
Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed
immediately by a STOP field.
SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
Internal SMBus Memory Register Set
The following table provides the SMBus slave interface register map values.
REGISTER NAME
Status/Command
VID LSB
VID MSB
PID LSB
PID MSB
DID LSB
DID MSB
Config Data Byte 1
Config Data Byte 2
Non-Removable
Devices
Port Disable (Self)
Port Disable (Bus)
Max Power (Self)
Max Power (Bus)
Hub Controller
Max Current (Self)
Hub Controller
Max Current (bus)
Power-on Time
Table 5.4 SMBus Slave Interface Register Map
HCMCS
HCMCB
MAXPS
MAXPB
ABBR
PWRT
STCD
CFG1
CFG2
VIDM
PIDM
DIDM
VIDL
PIDL
DIDL
NRD
PDS
PDB
BIT 7
(MSB)
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
21
BIT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
BIT
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
BIT
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
BIT
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BIT
Revision 1.3 (06-28-04)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(LSB)
BIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0