DSP201 Burr-Brown Corporation, DSP201 Datasheet
DSP201
Available stocks
Related parts for DSP201
DSP201 Summary of contents
Page 1
... Both the DSP201 and DSP202 are packaged in stan- dard, low-cost 28-pin plastic DIP packages. Each is offered in two performance grades to match applica- tion requirements. ...
Page 2
... < +5.1 – Serial; MSB first; 16/18-bit and Cascaded = +2 4mA 4mA +2.4 OH +4.75 +5 –5.25 –5 +4.75 +5 –5.25 – 365 0 –40 2 DSP201KP DSP202KP MAX MIN TYP MAX –85 –92 –88 * 0.004 0.004 * * * ...
Page 3
... OUT f = 1kHz, –20dB OUT f = 1kHz, –60dB OUT – Ambient Temperature (°C) SIGNAL-TO-(NOISE + DISTORTION) vs OUTPUT UPDATE RATE f = 0dB OUT 4 40 Output Update Rate (kHz) vs TEMPERATURE Gain Error – Ambient Temperature (°C) DSP201/202 100 400 0.3 0.2 0.1 0 –0.1 100 ® ...
Page 4
... OUT 11.5kHz OUT 2 The DSP201 and DSP202 are ESD (electrostatic discharge) sensitive devices, and normal standard precautions should be taken. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed ...
Page 5
... Motorola and TI DSP ICs. Tie LOW for use with AT&T DSP ICs. Select Word Length In. If HIGH, DSP201 accepts first 16 bits of data. If LOW, DSP201 accepts first 18 bits of data. Data Synchronization Output. Active HIGH when SSF is HIGH, active LOW when SSF is LOW. ...
Page 6
... DSP202 PIN CONFIGURATION V – MSBB 2 VOSB 3 AGNDB 4 VOUTB DSP202 RESET 8 SSF 9 SWL 10 SYNC 11 XCLK 12 SINA 13 SINB 14 ® DSP201/202 DSP202 PIN ASSIGNMENTS PIN # NAME 1 V – MSBB AGND 28 3 VOSB 27 DGND 4 AGNDB 5 VOUTB VPOT 25 8 ...
Page 7
... This clock can be as fast as 12MHz. The Data Transfer Clock can tolerate duty cycles from 40% to 60%. As indicated in the timing diagrams in Figure 1, either 16- or 18-bits of data will be clocked into the DSP201 or DSP202, or 32-bits will be clocked into the DSP202 in the OUTPUT VOLTAGE HEX ...
Page 8
... FIGURE 1. DSP201 and DSP202 Timing. ® DSP201/202 8 ...
Page 9
... D/As on the next Convert Command. If SWL is LOW, the DSP201 or DSP202 will clock 18 bits of data into the internal shift register after a Convert Com- mand, with the timing shown in Figure 1. Subsequent data on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) will be ignored ...
Page 10
... If external trims are not used, pins 23, 24, and 25 on the DSP201 should be left open, as should pins 2, 3, 23, 24 and 25 on the DSP202. These pins should not be decoupled with capacitors or tied to any specific potential, or the noise on the D/A outputs may increase ...
Page 11
... An alternative for calibrating on a bench is to tie SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) HIGH, and provide a Bit Clock and periodic Convert Commands. or 3FFFF This loads 1111...1111 (FFFF HEX output to 1LSB below 0V. Then periodically bring RESET (pin 8) LOW for at least two Convert Commands, which is the equivalent of loading all 0s, so the output is 0V ...
Page 12
... Offset Adjust 100k 2.2µF + –5V +5V 3.3k +5V + 2.2µF 0.01µF FIGURE 3. DSP202 Power Supply Connections and Optional Offset Voltage Adjustment. MSB Adjust Channel B 100k –5V 100k FIGURE 4. DSP202 Optional MSB Adjust Circuit. ® DSP201/202 DSP202 AGND – A 0.01µ VOSB AGNDB ...
Page 13
... A/Ds with easy to use interfacing logic that complement the DSP201 and DSP202. Figure 6 shows a single channel analog input and output system based on a DSP201 and a DSP101, and the minimal connections required to interface to a DSP IC. A pair of channels can be implemented using ...
Page 14
... CONV 16 CASC 9 SSF Sync Format Input 10 SWL Data Length 17 ENABLE 8 RESET +5V DIGITAL SIGNAL PROCESSOR DSP32C DSP16 DSP56001 in 16-bit Mode DSP56001 in 24-bit Mode TMS320C25 14 DSP201 12 XCLK 21 13 SIN VOUT ±3V Analog Output 11 SYNC 9 SSF 10 SWL 15 CONV *SSF **SWL LOW HIGH HIGH LOW ...
Page 15
... MSB bit first with SYNC in the Bit Mode. If the DSP56001 is programmed for 16-bit data words, SWL (pin 10) on the DSP201 or DSP202 needs to be tied HIGH to select the 16-bit Mode. In the DSP56001 24-bit mode, the DSP201 or DSP202 can be programmed to accept data lengths of 16-bits (with SWL HIGH) or 18-bits (with SWL LOW), and will ignore the trailing bits on the serial line ...
Page 16
... NOTES: (1) Sample rate on DSP102 and DSP202 may differ. (2) Analog Devices ADSP2101 may be used. SPORT1 and SPORT2 are used for serial MSB first communication. *See Burr-Brown DSP101/102 product data sheet for full description of this ADC. FIGURE 10. Two-Channel Analog Input and Output System with TMS320C30. ® DSP201/202 TTL Bit Clock DSP202 12 ...
Page 17
... CLKX FSX DX Conversion Rate Generator NOTE: FSX is programmed for external mode. FIGURE 12. Using DSP201 with TMS320C25. DSP56001 SSI Port Conversion Rate Generator NOTES: (1) DSP56001 programmed for MSB bit first. (2) For 16-bit data connect SWL to Logic 1; For 24-bit data connect SWL to Logic 0. ...
Page 18
... MSB first. Figure 14 shows the connections required to generate an analog output channel using an ADSP2105 with the DSP201. The same basic circuit can also be used to connect a DSP201 to the ADSP2101. Figure 6 indicates how to build a complete analog input and analog output system using either the ADSP2101 or ADSP2105 with a DSP201 and a Burr-Brown DSP101 A/D ...
Page 19
... DSP32C SIO OCK OLD DO OEN Conversion Rate Generator NOTES: DSP32C programmed for MSB bit first. Data length 16 bit. External OCK, ILD. FIGURE 15. Using DSP201 with DSP32C with 16-Bit Data Words. DSP32C SIO OCK OLD DO OEN Conversion Rate Generator NOTES: (1) DSP32C programmed for MSB bit first. (2) Data length 32 bits. External OCK, ILD. ...