DS12B887 Dallas Semiconductor, DS12B887 Datasheet
DS12B887
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DS12B887 Summary of contents
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... Periodic rates from 122 s to 500 ms – End of clock update cycle DESCRIPTION The DS12B887 Real Time Clock plus RAM is designed direct replacement for the DS1287A or DS12887A. The DS12B887 is identical in form, fit, and function to the DS1287A or DS12887A, with the excep- tion of RCLR, and has an additional 64 bytes of general purpose RAM ...
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... INCREMENT V CC nally forced to an inactive level regardless of the value the input pin. The DS12B887 is, therefore, write- protected. When the DS12B887 write-protected state, all inputs are ignored and all outputs are in a high is applied to the DS12B887 impedance state. When V ...
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... DS12B887 is less than 4.25 volts CC SQW OUTPUT SQW OUTPUT FREQUENCY None 256 Hz 128 Hz 8.192 kHz 4.096 kHz 2.048 kHz 1.024 kHz 512 Hz 256 Hz 128 ...
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... Write Enable signal (WE) on generic RAMs. CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the DS12B887 to be accessed. CS must be kept in the active state during RD and WR. Bus cycles which take place without asserting CS will latch addresses but no access will occur ...
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... ADDRESS MAP DS12B887 Figure BYTES 13 14 www.DataSheet4U.com 127 TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by read- ing the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten time, calendar, and alarm bytes can be either Binary or Binary-Coded Deci- mal (BCD) format ...
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... NONVOLATILE RAM The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the DS12B887. They can be used by the processor program as nonvol- atile memory and are fully available during the update cycle. INTERRUPTS The RTC plus RAM includes three separate, fully auto- matic sources of interrupt for a processor ...
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... IRQ pin is being driven low. Determination that the RTC initiated an interrupt is accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the DS12B887. The act of reading Register C clears all active flag bits and the IRQF bit. www.DataSheet4U.com OSCILLATOR CONTROL BITS When the DS12B887 is shipped from the factory, the internal oscillator is turned off ...
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... REGISTER C www.DataSheet4U.com t = Periodic interrupt time interval per Table Delay time before update cycle = 244 s. BUC REGISTERS The DS12B887 has four control registers which are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 BIT 6 BIT 5 UIP DV2 DV1 ...
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... When the AIE bit is set to zero, the AF bit does not initiate the IRQ signal. The internal functions of the DS12B887 do not affect the AIE bit. UIE The Update Ended Interrupt Enable (UIE) bit is a read/ write that enables the Update End Flag (UF) bit in Regis- ter C to assert IRQ ...
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... DS12B887 PF The Periodic Interrupt Flag (PF read-only bit which is set to a one when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate set to a one indepen- dent of the state of the PIE bit. When both PF and PIE are ones, the IRQ signal is active and will set the IRQF bit ...
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... All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However, standard versions of the DS12B887 are not exposed to environmental stresses, such as burn–in, that some industrial applications require. For specific reliability information on this product, please contact the factory in Dallas at (214) 450– ...
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... DS12B887 AC ELECTRICAL CHARACTERISTICS PARAMETER Cycle Time Pulse Width, DS/E Low or RD/WR High Pulse Width, DS/E High or RD/WR Low Input Rise and Fall Time www.DataSheet4U.com Chip Select Setup Time Before DS, WR Chip Select Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid Time to AS/ ...
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... DS12B887 BUS TIMING FOR WRITE CYCLE ALE (AS PIN) www.DataSheet4U.com RD (DS PIN) WR (R/W PIN) CS AD0–AD7 t CYC PW ASH t ASD t ASD t ASED AHL t t ASL DSW DS12B887 DHW 080895 13/16 ...
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... DS12B887 DS12B887 BUS TIMING FOR READ CYCLE ALE (AS PIN) www.DataSheet4U.com RD (DS PIN) WR (R/W PIN) CS AD0–AD7 DS12B887 IRQ RELEASE DELAY TIMING DS IRQ 080895 14/16 t CYC PW ASH t ASD t ASED ASD t DDR AHL t ASL t IRDS DHR ...
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... MIN 300 F t 100 REC SYMBOL MIN WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. DS12B887 REC TYP MAX UNITS NOTES 200 ms TYP MAX UNITS NOTES years 080895 15/16 ...
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... DS12B887 DS12B887 REAL TIME CLOCK PLUS RAM 24 1 www.DataSheet4U.com D 080895 16/ EQUAL SPACES AT .100 .010 TNA PKG 24-PIN NOTE: DIM MIN MAX A IN. 1.320 1.335 MM 33.53 33.91 B IN. 0.675 0.700 MM 17.15 17.78 C IN. 0.345 0.370 MM 8.76 9.40 D IN. 0.100 0.130 MM 2.54 3.30 E IN. 0.015 0.030 MM 0.38 0.76 F IN. ...