MCP6241R Microchip Technology Inc., MCP6241R Datasheet - Page 9

• Manufacturer Part Number: MCP6241R
• Description: 50 ?a, 550 Khz Rail-to-rail Op Am
• Manufacturer: Microchip Technology Inc.

FIGURE 4-4:
for Capacitive Loads.
After selecting R
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6241/2/4 SPICE macro
model are very helpful. Modify R
response is reasonable.
4.4
With this op amp, the power supply pin (V
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other nearby analog parts.
4.5
An unused op amp in a quad package (MCP6244)
should be configured as shown in Figure 4-5. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
FIGURE 4-5:
© 2005 Microchip Technology Inc.
1.E+04
1.E+03
1.E+02
V
¼ MCP6244 (A)
10k
100
DD
1k
1.E+01
10p
Supply Bypass
Unused Op Amps
Normalized Load Capacitance; C
ISO
V
DD
1.E+02
for your circuit, double-check the
100p
Recommended R
Unused Op Amps.
G
G
¼ MCP6244 (B)
N
N
= +1 V/V
1.E+03
ISO
+2 V/V
1n
’s value until the
V
L
/G
DD
ISO
N
(F)
1.E+04
Values
10n
DD
for
4.6
In applications where low input bias current is critical,
PCB (printed circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA of current to flow, which is greater than the
MCP6241/2/4 family’s bias current at 25°C (1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
FIGURE 4-6:
for Inverting Gain.
1.
2.
Non-inverting Gain and Unity-Gain Buffer:
a.
b.
Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a.
b.
PCB Surface Leakage
Connect the non-inverting pin (V
input with a wire that does not touch the
PCB surface.
Connect the guard ring to the inverting input
pin (V
common mode input voltage.
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the op
amp (e.g., V
Connect the inverting pin (V
with a wire that does not touch the PCB
surface.
IN
–). This biases the guard ring to the
V
MCP6241/2/4
IN
IN
Guard Ring
DD
+). This biases the guard ring
Example Guard Ring Layout
-
/2 or ground).
12
V
. A 5V difference would
IN
+
IN
DS21882C-page 9
–) to the input
IN
V
SS
+) to the