MCP4017 Microchip Technology Inc., MCP4017 Datasheet - Page 33

• Manufacturer Part Number: MCP4017
• Description: 7-bit Single I 2 C? Digital Pot With Volatile Memory In Sc70
• Manufacturer: Microchip Technology Inc.

5.0
A 2-wire I
digital potentiometer’s wiper register. The I
utilizes the SCL input pin and SDA input/output pin.
The I
• Slave mode of operation
• 7-bit addressing
• The following clock rate modes are supported:
• Support Multi-Master Applications
The serial clock is generated by the Master.
The I
specification. Phillips only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
for the MCP4017, MCP4018, and MCP4019 devices
are defined in this section of the Data Sheet.
Figure 5-1
FIGURE 5-1:
Configurations.
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
© 2009 Microchip Technology Inc.
- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s
Single I
Controller
2
2
C serial interface supports the following features.
Host
C Module is compatible with the Phillips I
SERIAL INTERFACE -
I
2
2
C serial protocol is used to write or read the
2
shows a typical I
C MODULE
C Bus Configuration
Device 1
Device 2
Typical Application I
2
C bus configurations.
Device 3
Device 4
2
Device n
C protocol
2
C Bus
2
C
5.1
I
functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to V
specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts the pull-up value for optimum system
performance.
Common pull-up values range from 1 k
~10 k
higher values to minimize current losses during
communication but these applications also typically
utilize lower V
The SDA and SCL float (are not driving) when the
device is powered down.
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.
5.1.1
The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
2
C specifications require active low, passive high
Ω
. Power sensitive applications tend to choose
I
SS
2
C I/O Considerations
SLOPE CONTROL
(common) with a pull-up resistor. The
DD
MCP4017/18/19
.
DS22147A-page 33
Ω
to a max of